Zhichun Hua db14f11dfe armv8/fsl-lsch3: Fix TCR_EL3 for the final MMU setup. ...

When final MMU table is setup in DDR, TCR attributes must match
those of the memroy for cacheability and shareability.

Signed-off-by: Zhichun Hua <zhichun.hua@freescale.com>
Signed-off-by: York Sun <yorksun@freescale.com>

2015-07-20 11:44:40 -07:00

..

fsl-lsch3

armv8/fsl-lsch3: Fix TCR_EL3 for the final MMU setup.

2015-07-20 11:44:40 -07:00

zynqmp

zynqmp: Add support for emulation platform - Veloce

2015-04-29 11:19:03 +02:00

cache_v8.c

armv8/fsl-lsch3: Convert flushing L3 to assembly to avoid using stack

2015-02-24 13:08:46 -08:00

cache.S

remove unnecessary version.h includes

2015-03-24 10:50:50 -04:00

config.mk

ARM: move -march=* and -mtune= options to arch/arm/Makefile

2015-03-27 16:55:22 +01:00

cpu.c

arm64: core support

2014-01-09 16:08:44 +01:00

exceptions.S

remove unnecessary version.h includes

2015-03-24 10:50:50 -04:00

generic_timer.c

armv8/fsl-lsch3: Implement workaround for erratum A008585

2015-04-23 08:55:54 -07:00

Kconfig

armv8/vexpress64: make multientry conditional

2015-03-09 11:13:29 -04:00

Makefile

arm64: Add Xilinx ZynqMP support

2015-03-02 18:41:54 +01:00

start.S

arm/errata: Update required bits for A57 cores erratas

2015-07-20 11:44:35 -07:00

tlb.S

remove unnecessary version.h includes

2015-03-24 10:50:50 -04:00

transition.S

remove unnecessary version.h includes

2015-03-24 10:50:50 -04:00

u-boot-spl.lds

armv8/ls2085aqds: NAND boot support

2015-04-23 16:46:50 -07:00

u-boot.lds

arm64: core support

2014-01-09 16:08:44 +01:00