Bin Meng 62ce0a02f9 riscv: andes_plic: Fix riscv_get_ipi() mask ...

Current logic in riscv_get_ipi() for Andes PLICSW does not look
correct. The mask to test IPI pending bits for a hart should be
left shifted by (8 * gd->arch.boot_hart), just the same as what
is done in riscv_send_ipi().

Fixes: 8b3e97badf97 ("riscv: add functions for reading the IPI status")
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>
Tested-by: Rick Chen <rick@andestech.com>

2021-06-17 09:39:46 +08:00

..

cpu

riscv: cpu: fu740: clear feature disable CSR

2021-05-31 16:35:55 +08:00

dts

riscv: ae350: dts: Add missing "u-boot, dm-spl" for SPL config

2021-06-17 09:39:08 +08:00

include/asm

riscv: cpu: fu740: Add support for cpu fu740

2021-05-31 16:35:53 +08:00

lib

riscv: andes_plic: Fix riscv_get_ipi() mask

2021-06-17 09:39:46 +08:00

config.mk

kconfig / kbuild: Re-sync with Linux 4.19

2020-04-10 11:18:32 -04:00

Kconfig

board: sifive: add HiFive Unmatched board support

2021-05-31 16:35:55 +08:00

Makefile

riscv: add Kconfig entries for the code model

2018-12-18 09:56:26 +08:00