Michal Simek e90d2659e4 serial: zynq: Write chars till output fifo is full
Change logic and put char to fifo till there is a space in output fifo.
Origin logic was that output fifo needs to be empty. It means only one
char was in output queue.
Also remove unused ZYNQ_UART_SR_TXEMPTY macro.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-06-15 08:54:05 +02:00
..
2018-05-26 18:19:17 -04:00
2018-02-23 10:40:50 -05:00