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3b95902d47
Add support for clocks needed by MACs to ast2500 clock driver.
The clocks are D2-PLL, which is used by both MACs and PCLK_MAC1 and
PCLK_MAC2 for MAC1 and MAC2 respectively.
The rate of D2-PLL is hardcoded to 250MHz -- the value used in Aspeed
SDK. It is not entirely clear from the datasheet how this clock is used
by MACs, so not clear if the rate would ever need to be different. So,
for now, hardcoding it is probably safer.
The rate of PCLK_MAC{1,2} is chosen based on MAC speed selected through
hardware strapping.
So, the network driver would only need to enable these clocks, no need
to configure the rate.
Signed-off-by: Maxim Sloyko <maxims@google.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
32 lines
555 B
C
32 lines
555 B
C
/*
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* Copyright 2016 Google Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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/* Core Clocks */
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#define PLL_HPLL 1
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#define PLL_DPLL 2
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#define PLL_D2PLL 3
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#define PLL_MPLL 4
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#define ARMCLK 5
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/* Bus Clocks, derived from core clocks */
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#define BCLK_PCLK 101
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#define BCLK_LHCLK 102
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#define BCLK_MACCLK 103
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#define BCLK_SDCLK 104
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#define BCLK_ARMCLK 105
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#define MCLK_DDR 201
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/* Special clocks */
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#define PCLK_UART1 501
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#define PCLK_UART2 502
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#define PCLK_UART3 503
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#define PCLK_UART4 504
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#define PCLK_UART5 505
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#define PCLK_MAC1 506
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#define PCLK_MAC2 507
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