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2c7920afaf
Use the standard lowercase "x" capitalization that other Freescale architectures use for CPU defines to prevent confusion and errors Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
129 lines
3.7 KiB
Plaintext
129 lines
3.7 KiB
Plaintext
Freescale MPC832XEMDS Board
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-----------------------------------------
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1. Board Switches and Jumpers
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1.0 There are five Dual-In-Line Packages(DIP) Switches on MPC832XE SYS board
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For some reason, the HW designers describe the switch settings
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in terms of 0 and 1, and then map that to physical switches where
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the label "On" refers to logic 0 and "Off" is logic 1.
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Switch bits are numbered 1 through, like, 4 6 8 or 10, but the
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bits may contribute to signals that are numbered based at 0,
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and some of those signals may be high-bit-number-0 too. Heed
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well the names and labels and do not get confused.
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"Off" == 1
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"On" == 0
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SW3 is switch 18 as silk-screened onto the board.
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SW4[8] is the bit labled 8 on Switch 4.
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SW5[1:6] refers to bits labeled 1 through 6 in order on switch 5.
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SW6[7:1] refers to bits labeled 7 through 1 in order on switch 6.
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SW7[1:8]= 0000_0001 refers to bits labeled 1 through 6 is set as "On"
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and bits labeled 8 is set as "Off".
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1.1 For the MPC832XEMDS PROTO Board
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First, make sure the board default setting is consistent with the document
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shipped with your board. Then apply the following setting:
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SW3[1-8]= 0000_1000 (core PLL setting, core enable)
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SW4[1-8]= 0001_0010 (Flash boot on local bus, system PLL setting)
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SW5[1-8]= 0010_0110 (Boot from high end)
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SW6[1-8]= 0011_0100 (Flash boot on 16 bit local bus)
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SW7[1-8]= 1000_0011 (QE PLL setting)
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ENET3/4 MII mode settings:
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J1 1-2 (ETH3_TXER)
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J2 2-3 (MII mode)
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J3 2-3 (MII mode)
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J4 2-3 (ADSL clockOscillator)
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J5 1-2 (ETH4_TXER)
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J6 2-3 (ClockOscillator)
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JP1 removed (don't force PORESET)
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JP2 mounted (ETH4/2 MII)
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JP3 mounted (ETH3 MII)
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JP4 mounted (HRCW from BCSR)
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ENET3/4 RMII mode settings:
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J1 1-2 (ETH3_TXER)
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J2 1-2 (RMII mode)
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J3 1-2 (RMII mode)
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J4 2-3 (ADSL clockOscillator)
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J5 1-2 (ETH4_TXER)
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J6 2-3 (ClockOscillator)
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JP1 removed (don't force PORESET)
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JP2 removed (ETH4/2 RMII)
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JP3 removed (ETH3 RMII)
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JP4 removed (HRCW from FLASH)
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on board Oscillator: 66M
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2. Memory Map
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2.1 The memory map should look pretty much like this:
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0x0000_0000 0x7fff_ffff DDR 2G
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0x8000_0000 0x8fff_ffff PCI MEM prefetch 256M
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0x9000_0000 0x9fff_ffff PCI MEM non-prefetch 256M
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0xc000_0000 0xdfff_ffff Empty 512M
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0xe000_0000 0xe01f_ffff Int Mem Reg Space 2M
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0xe020_0000 0xe02f_ffff Empty 1M
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0xe030_0000 0xe03f_ffff PCI IO 1M
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0xe040_0000 0xefff_ffff Empty 252M
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0xf400_0000 0xf7ff_ffff Empty 64M
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0xf800_0000 0xf800_7fff BCSR on CS1 32K
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0xf800_8000 0xf800_ffff PIB CS2 32K
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0xf801_0000 0xf801_7fff PIB CS3 32K
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0xfe00_0000 0xfeff_ffff FLASH on CS0 16M
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3. Definitions
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3.1 Explanation of NEW definitions in:
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include/configs/MPC832XEPB.h
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CONFIG_MPC83xx MPC83xx family for MPC8349, MPC8360 and MPC832x
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CONFIG_MPC832x MPC832x specific
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CONFIG_MPC832XEMDS MPC832XEMDS board specific
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4. Compilation
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Assuming you're using BASH shell:
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export CROSS_COMPILE=your-cross-compile-prefix
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cd u-boot
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make distclean
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make MPC832XEMDS_config
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make
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MPC832x support PCI 33MHz and PCI 66MHz, to make u-boot support PCI:
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1)Make sure the DIP SW support PCI mode as described in Section 1.1.
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2)To Make U-Boot image support PCI 33MHz, use
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Make MPC832XEMDS_HOST_33_config
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3)To Make U-Boot image support PCI 66MHz, use
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Make MPC832XEMDS_HOST_66M_config
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5. Downloading and Flashing Images
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5.0 Download over network:
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tftp 10000 u-boot.bin
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5.1 Reflash U-boot Image using U-boot
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tftp 20000 u-boot.bin
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protect off fe000000 fe0fffff
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erase fe000000 fe0fffff
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cp.b 20000 fe000000 xxxx
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You have to supply the correct byte count with 'xxxx' from the TFTP result log.
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Maybe 3ffff will work too, that corresponds to the erased sectors.
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6. Notes
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1) The console baudrate for MPC832XEMDS is 115200bps.
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