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e064db5fe7
STM32F4/F7 and H7 series doesn't have a clear reset register, so
set_clr field must be set to false.
Fixes: 0994a627c2 ("reset: stm32mp25: add stm32mp25 reset driver")
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
44 lines
1.2 KiB
C
44 lines
1.2 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause
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/*
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* Copyright (C) 2017, STMicroelectronics - All Rights Reserved
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* Author(s): Patrice Chotard, <patrice.chotard@foss.st.com> for STMicroelectronics.
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*/
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#include <dm.h>
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#include "stm32-reset-core.h"
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/* Timeout for deassert */
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#define STM32_DEASSERT_TIMEOUT_US 10000
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static const struct stm32_reset_cfg *stm32_get_reset_line(struct reset_ctl *reset_ctl)
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{
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struct stm32_reset_priv *priv = dev_get_priv(reset_ctl->dev);
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struct stm32_reset_cfg *ptr_line = &priv->reset_line;
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int bank = (reset_ctl->id / (sizeof(u32) * BITS_PER_BYTE)) * 4;
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int offset = reset_ctl->id % (sizeof(u32) * BITS_PER_BYTE);
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ptr_line->offset = bank;
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ptr_line->bit_idx = offset;
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ptr_line->set_clr = false;
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return ptr_line;
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}
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static const struct stm32_reset_data stm32_reset_data = {
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.get_reset_line = stm32_get_reset_line,
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.reset_us = STM32_DEASSERT_TIMEOUT_US,
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};
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static int stm32_reset_probe(struct udevice *dev)
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{
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return stm32_reset_core_probe(dev, &stm32_reset_data);
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}
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U_BOOT_DRIVER(stm32_rcc_reset) = {
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.name = "stm32_rcc_reset",
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.id = UCLASS_RESET,
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.probe = stm32_reset_probe,
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.priv_auto = sizeof(struct stm32_reset_priv),
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.ops = &stm32_reset_ops,
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};
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