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d678a59d2d
When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
140 lines
3.0 KiB
C
140 lines
3.0 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2018 Álvaro Fernández Rojas <noltari@gmail.com>
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*
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* Derived from linux/arch/mips/bcm63xx/usb-common.c:
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* Copyright 2008 Maxime Bizon <mbizon@freebox.fr>
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* Copyright 2013 Florian Fainelli <florian@openwrt.org>
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*/
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#include <common.h>
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#include <clk.h>
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#include <dm.h>
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#include <generic-phy.h>
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#include <log.h>
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#include <malloc.h>
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#include <power-domain.h>
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#include <reset.h>
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#include <asm/io.h>
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#include <dm/device.h>
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#include <linux/bitops.h>
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#include <linux/delay.h>
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/* USBH Setup register */
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#define USBH_SETUP_REG 0x00
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#define USBH_SETUP_IOC BIT(4)
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/* USBH PLL Control register */
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#define USBH_PLL_REG 0x04
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#define USBH_PLL_SUSP_EN BIT(27)
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#define USBH_PLL_IDDQ_PWRDN BIT(31)
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/* USBH Swap Control register */
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#define USBH_SWAP_REG 0x0c
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#define USBH_SWAP_OHCI_DATA BIT(0)
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#define USBH_SWAP_OHCI_ENDIAN BIT(1)
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#define USBH_SWAP_EHCI_DATA BIT(3)
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#define USBH_SWAP_EHCI_ENDIAN BIT(4)
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/* USBH Sim Control register */
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#define USBH_SIM_REG 0x20
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#define USBH_SIM_LADDR BIT(5)
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struct bcm6318_usbh_priv {
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void __iomem *regs;
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};
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static int bcm6318_usbh_init(struct phy *phy)
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{
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struct bcm6318_usbh_priv *priv = dev_get_priv(phy->dev);
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/* enable pll control susp */
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setbits_be32(priv->regs + USBH_PLL_REG, USBH_PLL_SUSP_EN);
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/* configure to work in native cpu endian */
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clrsetbits_be32(priv->regs + USBH_SWAP_REG,
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USBH_SWAP_EHCI_ENDIAN | USBH_SWAP_OHCI_ENDIAN,
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USBH_SWAP_EHCI_DATA | USBH_SWAP_OHCI_DATA);
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/* setup config */
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setbits_be32(priv->regs + USBH_SETUP_REG, USBH_SETUP_IOC);
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/* disable pll control pwrdn */
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clrbits_be32(priv->regs + USBH_PLL_REG, USBH_PLL_IDDQ_PWRDN);
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/* sim control config */
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setbits_be32(priv->regs + USBH_SIM_REG, USBH_SIM_LADDR);
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return 0;
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}
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static struct phy_ops bcm6318_usbh_ops = {
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.init = bcm6318_usbh_init,
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};
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static const struct udevice_id bcm6318_usbh_ids[] = {
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{ .compatible = "brcm,bcm6318-usbh" },
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{ /* sentinel */ }
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};
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static int bcm6318_usbh_probe(struct udevice *dev)
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{
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struct bcm6318_usbh_priv *priv = dev_get_priv(dev);
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struct power_domain pwr_dom;
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struct reset_ctl rst_ctl;
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struct clk clk;
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int ret;
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priv->regs = dev_remap_addr(dev);
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if (!priv->regs)
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return -EINVAL;
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/* enable usbh clock */
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ret = clk_get_by_name(dev, "usbh", &clk);
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if (ret < 0)
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return ret;
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ret = clk_enable(&clk);
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if (ret < 0)
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return ret;
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/* enable power domain */
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ret = power_domain_get(dev, &pwr_dom);
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if (ret < 0)
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return ret;
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ret = power_domain_on(&pwr_dom);
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if (ret < 0)
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return ret;
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ret = power_domain_free(&pwr_dom);
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if (ret < 0)
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return ret;
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/* perform reset */
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ret = reset_get_by_index(dev, 0, &rst_ctl);
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if (ret < 0)
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return ret;
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ret = reset_deassert(&rst_ctl);
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if (ret < 0)
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return ret;
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ret = reset_free(&rst_ctl);
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if (ret < 0)
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return ret;
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mdelay(100);
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return 0;
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}
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U_BOOT_DRIVER(bcm6318_usbh) = {
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.name = "bcm6318-usbh",
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.id = UCLASS_PHY,
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.of_match = bcm6318_usbh_ids,
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.ops = &bcm6318_usbh_ops,
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.priv_auto = sizeof(struct bcm6318_usbh_priv),
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.probe = bcm6318_usbh_probe,
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};
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