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d678a59d2d
When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
122 lines
3.0 KiB
C
122 lines
3.0 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* pic32_mdio.c: PIC32 MDIO/MII driver, part of pic32_eth.c.
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*
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* Copyright 2015 Microchip Inc.
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* Purna Chandra Mandal <purna.mandal@microchip.com>
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*/
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#include <common.h>
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#include <phy.h>
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#include <miiphy.h>
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#include <errno.h>
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#include <wait_bit.h>
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#include <asm/io.h>
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#include <linux/delay.h>
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#include "pic32_eth.h"
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static int pic32_mdio_write(struct mii_dev *bus,
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int addr, int dev_addr,
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int reg, u16 value)
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{
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u32 v;
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struct pic32_mii_regs *mii_regs = bus->priv;
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/* Wait for the previous operation to finish */
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wait_for_bit_le32(&mii_regs->mind.raw, MIIMIND_BUSY,
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false, CONFIG_SYS_HZ, true);
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/* Put phyaddr and regaddr into MIIMADD */
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v = (addr << MIIMADD_PHYADDR_SHIFT) | (reg & MIIMADD_REGADDR);
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writel(v, &mii_regs->madr.raw);
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/* Initiate a write command */
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writel(value, &mii_regs->mwtd.raw);
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/* Wait 30 clock cycles for busy flag to be set */
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udelay(12);
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/* Wait for write to complete */
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wait_for_bit_le32(&mii_regs->mind.raw, MIIMIND_BUSY,
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false, CONFIG_SYS_HZ, true);
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return 0;
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}
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static int pic32_mdio_read(struct mii_dev *bus, int addr, int devaddr, int reg)
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{
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u32 v;
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struct pic32_mii_regs *mii_regs = bus->priv;
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/* Wait for the previous operation to finish */
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wait_for_bit_le32(&mii_regs->mind.raw, MIIMIND_BUSY,
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false, CONFIG_SYS_HZ, true);
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/* Put phyaddr and regaddr into MIIMADD */
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v = (addr << MIIMADD_PHYADDR_SHIFT) | (reg & MIIMADD_REGADDR);
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writel(v, &mii_regs->madr.raw);
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/* Initiate a read command */
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writel(MIIMCMD_READ, &mii_regs->mcmd.raw);
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/* Wait 30 clock cycles for busy flag to be set */
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udelay(12);
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/* Wait for read to complete */
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wait_for_bit_le32(&mii_regs->mind.raw,
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MIIMIND_NOTVALID | MIIMIND_BUSY,
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false, CONFIG_SYS_HZ, false);
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/* Clear the command register */
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writel(0, &mii_regs->mcmd.raw);
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/* Grab the value read from the PHY */
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v = readl(&mii_regs->mrdd.raw);
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return v;
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}
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static int pic32_mdio_reset(struct mii_dev *bus)
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{
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struct pic32_mii_regs *mii_regs = bus->priv;
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/* Reset MII (due to new addresses) */
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writel(MIIMCFG_RSTMGMT, &mii_regs->mcfg.raw);
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/* Wait for the operation to finish */
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wait_for_bit_le32(&mii_regs->mind.raw, MIIMIND_BUSY,
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false, CONFIG_SYS_HZ, true);
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/* Clear reset bit */
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writel(0, &mii_regs->mcfg);
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/* Wait for the operation to finish */
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wait_for_bit_le32(&mii_regs->mind.raw, MIIMIND_BUSY,
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false, CONFIG_SYS_HZ, true);
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/* Set the MII Management Clock (MDC) - no faster than 2.5 MHz */
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writel(MIIMCFG_CLKSEL_DIV40, &mii_regs->mcfg.raw);
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/* Wait for the operation to finish */
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wait_for_bit_le32(&mii_regs->mind.raw, MIIMIND_BUSY,
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false, CONFIG_SYS_HZ, true);
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return 0;
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}
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int pic32_mdio_init(const char *name, ulong ioaddr)
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{
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struct mii_dev *bus;
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bus = mdio_alloc();
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if (!bus) {
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printf("Failed to allocate PIC32-MDIO bus\n");
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return -ENOMEM;
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}
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bus->read = pic32_mdio_read;
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bus->write = pic32_mdio_write;
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bus->reset = pic32_mdio_reset;
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strncpy(bus->name, name, sizeof(bus->name));
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bus->priv = (void *)ioaddr;
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return mdio_register(bus);
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}
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