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https://source.denx.de/u-boot/u-boot.git
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d678a59d2d
When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
150 lines
3.6 KiB
C
150 lines
3.6 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2020 NXP
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*/
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#include <common.h>
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#include <dm.h>
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#include <errno.h>
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#include <miiphy.h>
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#include <asm/io.h>
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#include <fsl_memac.h>
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#ifdef CONFIG_SYS_MEMAC_LITTLE_ENDIAN
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#define memac_out_32(a, v) out_le32(a, v)
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#define memac_clrbits_32(a, v) clrbits_le32(a, v)
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#define memac_setbits_32(a, v) setbits_le32(a, v)
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#else
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#define memac_out_32(a, v) out_be32(a, v)
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#define memac_clrbits_32(a, v) clrbits_be32(a, v)
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#define memac_setbits_32(a, v) setbits_be32(a, v)
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#endif
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static u32 memac_in_32(u32 *reg)
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{
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#ifdef CONFIG_SYS_MEMAC_LITTLE_ENDIAN
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return in_le32(reg);
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#else
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return in_be32(reg);
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#endif
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}
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struct fsl_ls_mdio_priv {
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void *regs_base;
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};
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static u32 fsl_ls_mdio_setup_operation(struct udevice *dev, int addr, int devad,
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int reg)
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{
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struct fsl_ls_mdio_priv *priv = dev_get_priv(dev);
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struct memac_mdio_controller *regs;
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u32 mdio_ctl;
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u32 c45 = 1;
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regs = (struct memac_mdio_controller *)(priv->regs_base);
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if (devad == MDIO_DEVAD_NONE) {
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c45 = 0; /* clause 22 */
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devad = reg & 0x1f;
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memac_clrbits_32(®s->mdio_stat, MDIO_STAT_ENC);
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} else {
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memac_setbits_32(®s->mdio_stat, MDIO_STAT_ENC);
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}
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/* Wait till the bus is free */
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while ((memac_in_32(®s->mdio_stat)) & MDIO_STAT_BSY)
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;
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/* Set the Port and Device Addrs */
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mdio_ctl = MDIO_CTL_PORT_ADDR(addr) | MDIO_CTL_DEV_ADDR(devad);
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memac_out_32(®s->mdio_ctl, mdio_ctl);
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/* Set the register address */
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if (c45)
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memac_out_32(®s->mdio_addr, reg & 0xffff);
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/* Wait till the bus is free */
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while ((memac_in_32(®s->mdio_stat)) & MDIO_STAT_BSY)
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;
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return mdio_ctl;
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}
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static int dm_fsl_ls_mdio_read(struct udevice *dev, int addr,
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int devad, int reg)
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{
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struct fsl_ls_mdio_priv *priv = dev_get_priv(dev);
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struct memac_mdio_controller *regs;
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u32 mdio_ctl;
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regs = (struct memac_mdio_controller *)(priv->regs_base);
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mdio_ctl = fsl_ls_mdio_setup_operation(dev, addr, devad, reg);
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/* Initiate the read */
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mdio_ctl |= MDIO_CTL_READ;
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memac_out_32(®s->mdio_ctl, mdio_ctl);
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/* Wait till the MDIO write is complete */
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while ((memac_in_32(®s->mdio_stat)) & MDIO_STAT_BSY)
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;
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/* Return all Fs if nothing was there */
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if (memac_in_32(®s->mdio_stat) & MDIO_STAT_RD_ER)
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return 0xffff;
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return memac_in_32(®s->mdio_data) & 0xffff;
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}
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static int dm_fsl_ls_mdio_write(struct udevice *dev, int addr, int devad,
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int reg, u16 val)
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{
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struct fsl_ls_mdio_priv *priv = dev_get_priv(dev);
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struct memac_mdio_controller *regs;
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regs = (struct memac_mdio_controller *)(priv->regs_base);
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fsl_ls_mdio_setup_operation(dev, addr, devad, reg);
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/* Write the value to the register */
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memac_out_32(®s->mdio_data, MDIO_DATA(val));
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/* Wait till the MDIO write is complete */
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while ((memac_in_32(®s->mdio_stat)) & MDIO_STAT_BSY)
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;
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return 0;
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}
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static const struct mdio_ops fsl_ls_mdio_ops = {
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.read = dm_fsl_ls_mdio_read,
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.write = dm_fsl_ls_mdio_write,
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};
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static int fsl_ls_mdio_probe(struct udevice *dev)
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{
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struct fsl_ls_mdio_priv *priv = dev_get_priv(dev);
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struct memac_mdio_controller *regs;
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priv->regs_base = dev_read_addr_ptr(dev);
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if (!priv->regs_base)
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return -ENODEV;
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regs = (struct memac_mdio_controller *)(priv->regs_base);
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memac_setbits_32(®s->mdio_stat,
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MDIO_STAT_CLKDIV(258) | MDIO_STAT_NEG);
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return 0;
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}
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static const struct udevice_id fsl_ls_mdio_of_ids[] = {
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{ .compatible = "fsl,ls-mdio" },
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};
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U_BOOT_DRIVER(fsl_ls_mdio) = {
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.name = "fsl_ls_mdio",
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.id = UCLASS_MDIO,
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.of_match = fsl_ls_mdio_of_ids,
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.probe = fsl_ls_mdio_probe,
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.ops = &fsl_ls_mdio_ops,
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.priv_auto = sizeof(struct fsl_ls_mdio_priv),
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};
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