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d678a59d2d
When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
167 lines
4.4 KiB
C
167 lines
4.4 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2021 BayLibre, SAS
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <dm.h>
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#include <phy.h>
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#include "designware.h"
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#include <dm/device_compat.h>
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#include <linux/err.h>
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#define ETH_REG_0 0x0
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#define ETH_REG_1 0x4
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#define ETH_REG_2 0x18
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#define ETH_REG_3 0x1c
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#define GX_ETH_REG_0_PHY_INTF BIT(0)
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#define GX_ETH_REG_0_TX_PHASE(x) (((x) & 3) << 5)
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#define GX_ETH_REG_0_TX_RATIO(x) (((x) & 7) << 7)
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#define GX_ETH_REG_0_PHY_CLK_EN BIT(10)
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#define GX_ETH_REG_0_INVERT_RMII_CLK BIT(11)
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#define GX_ETH_REG_0_CLK_EN BIT(12)
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#define AXG_ETH_REG_0_PHY_INTF_RGMII BIT(0)
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#define AXG_ETH_REG_0_PHY_INTF_RMII BIT(2)
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#define AXG_ETH_REG_0_TX_PHASE(x) (((x) & 3) << 5)
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#define AXG_ETH_REG_0_TX_RATIO(x) (((x) & 7) << 7)
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#define AXG_ETH_REG_0_PHY_CLK_EN BIT(10)
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#define AXG_ETH_REG_0_INVERT_RMII_CLK BIT(11)
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#define AXG_ETH_REG_0_CLK_EN BIT(12)
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struct dwmac_meson8b_plat {
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struct dw_eth_pdata dw_eth_pdata;
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int (*dwmac_setup)(struct udevice *dev, struct eth_pdata *edata);
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void *regs;
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};
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static int dwmac_meson8b_of_to_plat(struct udevice *dev)
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{
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struct dwmac_meson8b_plat *pdata = dev_get_plat(dev);
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pdata->regs = dev_read_addr_index_ptr(dev, 1);
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if (!pdata->regs)
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return -EINVAL;
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pdata->dwmac_setup = (void *)dev_get_driver_data(dev);
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if (!pdata->dwmac_setup)
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return -EINVAL;
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return designware_eth_of_to_plat(dev);
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}
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static int dwmac_setup_axg(struct udevice *dev, struct eth_pdata *edata)
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{
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struct dwmac_meson8b_plat *plat = dev_get_plat(dev);
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switch (edata->phy_interface) {
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case PHY_INTERFACE_MODE_RGMII:
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case PHY_INTERFACE_MODE_RGMII_ID:
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/* Set RGMII mode */
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setbits_le32(plat->regs + ETH_REG_0, AXG_ETH_REG_0_PHY_INTF_RGMII |
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AXG_ETH_REG_0_TX_PHASE(1) |
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AXG_ETH_REG_0_TX_RATIO(4) |
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AXG_ETH_REG_0_PHY_CLK_EN |
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AXG_ETH_REG_0_CLK_EN);
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break;
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case PHY_INTERFACE_MODE_RGMII_RXID:
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case PHY_INTERFACE_MODE_RGMII_TXID:
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/* TOFIX: handle amlogic,tx-delay-ns & rx-internal-delay-ps from DT */
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setbits_le32(plat->regs + ETH_REG_0, AXG_ETH_REG_0_PHY_INTF_RGMII |
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AXG_ETH_REG_0_TX_RATIO(4) |
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AXG_ETH_REG_0_PHY_CLK_EN |
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AXG_ETH_REG_0_CLK_EN);
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break;
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case PHY_INTERFACE_MODE_RMII:
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/* Set RMII mode */
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out_le32(plat->regs + ETH_REG_0, AXG_ETH_REG_0_PHY_INTF_RMII |
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AXG_ETH_REG_0_INVERT_RMII_CLK |
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AXG_ETH_REG_0_CLK_EN);
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break;
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default:
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dev_err(dev, "Unsupported PHY mode\n");
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return -EINVAL;
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}
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return 0;
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}
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static int dwmac_setup_gx(struct udevice *dev, struct eth_pdata *edata)
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{
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struct dwmac_meson8b_plat *plat = dev_get_plat(dev);
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switch (edata->phy_interface) {
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case PHY_INTERFACE_MODE_RGMII:
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case PHY_INTERFACE_MODE_RGMII_ID:
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/* Set RGMII mode */
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setbits_le32(plat->regs + ETH_REG_0, GX_ETH_REG_0_PHY_INTF |
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GX_ETH_REG_0_TX_PHASE(1) |
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GX_ETH_REG_0_TX_RATIO(4) |
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GX_ETH_REG_0_PHY_CLK_EN |
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GX_ETH_REG_0_CLK_EN);
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break;
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case PHY_INTERFACE_MODE_RGMII_RXID:
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case PHY_INTERFACE_MODE_RGMII_TXID:
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/* TOFIX: handle amlogic,tx-delay-ns & rx-internal-delay-ps from DT */
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setbits_le32(plat->regs + ETH_REG_0, GX_ETH_REG_0_PHY_INTF |
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GX_ETH_REG_0_TX_RATIO(4) |
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GX_ETH_REG_0_PHY_CLK_EN |
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GX_ETH_REG_0_CLK_EN);
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break;
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case PHY_INTERFACE_MODE_RMII:
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/* Set RMII mode */
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out_le32(plat->regs + ETH_REG_0, GX_ETH_REG_0_INVERT_RMII_CLK |
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GX_ETH_REG_0_CLK_EN);
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if (!IS_ENABLED(CONFIG_MESON_GXBB))
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writel(0x10110181, plat->regs + ETH_REG_2);
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break;
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default:
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dev_err(dev, "Unsupported PHY mode\n");
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return -EINVAL;
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}
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return 0;
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}
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static int dwmac_meson8b_probe(struct udevice *dev)
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{
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struct dwmac_meson8b_plat *pdata = dev_get_plat(dev);
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struct eth_pdata *edata = &pdata->dw_eth_pdata.eth_pdata;
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int ret;
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ret = pdata->dwmac_setup(dev, edata);
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if (ret)
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return ret;
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return designware_eth_probe(dev);
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}
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static const struct udevice_id dwmac_meson8b_ids[] = {
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{ .compatible = "amlogic,meson-gxbb-dwmac", .data = (ulong)dwmac_setup_gx },
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{ .compatible = "amlogic,meson-g12a-dwmac", .data = (ulong)dwmac_setup_axg },
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{ .compatible = "amlogic,meson-axg-dwmac", .data = (ulong)dwmac_setup_axg },
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{ }
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};
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U_BOOT_DRIVER(dwmac_meson8b) = {
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.name = "dwmac_meson8b",
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.id = UCLASS_ETH,
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.of_match = dwmac_meson8b_ids,
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.of_to_plat = dwmac_meson8b_of_to_plat,
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.probe = dwmac_meson8b_probe,
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.ops = &designware_eth_ops,
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.priv_auto = sizeof(struct dw_eth_dev),
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.plat_auto = sizeof(struct dwmac_meson8b_plat),
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.flags = DM_FLAG_ALLOC_PRIV_DMA,
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};
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