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* Implement the EVT_SIGNAL_VIRTUAL_ADDRESS_CHANGE event. * Address errors of type -Werror=address-of-packed-member when building with GCC9.1 * Fix an error when adding memory add addres 0x00000000. * Rework some code comments for Sphinx compliance. -----BEGIN PGP SIGNATURE----- iQIzBAABCAAdFiEEbcT5xx8ppvoGt20zxIHbvCwFGsQFAl0vSQEACgkQxIHbvCwF GsQfxQ//d/i5Ix7V5rtm9U1ew2lkaQw5O1/E//Ta//0AeWLaEnFf0ln1Fx5jLF6E f70uE6iDRgnxfZWD/rnCqv7HZrokpy3GuXnUfAZTgEvsngqicw8dAAU9Ql9Q62i9 N302GhaCGkbBp3MBOLRBXJmKuTnnzfU7jkeYo1tZbZe3AoqSNtI8ND86DHSotuUM 9Ck5367LdcG5O86N8gIxBtCcnthq94GgS/tY69iuPhhKqN3oV6MbzjqmI4wtkVH6 RhJSQspTsmyKTSivbcgpgIPXJJnTwh0nZcQWmzC81ehU3LF9i1M1J4SAqsZ7kpgt jWY959iXnd7iNfwFiCTLpf+mDrviyPzntt/aE8ras5IwbQdiwZONeQ/mhkP2Snoo RDX+dB3JqpyO/T+4uMdq+2saYBtKZ9CUKclqqh/xwvv5Bs63qHGC3KKYnjQx1sKA k5QD3XSOPDLYbqQBIcgiB9T5TWkO1igJVEWRxPtExl31DTkSXy6f7G1F7sZ+Ey+5 gugIhNeTCme4a9bSIc7FjFaZSvPR2SNd8azUkSfso6Vqd9bNRShBF7pImlrCRmj8 Xc0sknW824LOdeM6ZC54J7lYKyLfL3HljzYSiM7KExt21mAjNHWXt312hINr6SOA gz+/Osdyrv8GniP86Zw3kACto6Chaw51PEV1WReYPT3LNwinvoU= =aj4j -----END PGP SIGNATURE----- Merge tag 'efi-2019-10-rc1-2' of https://gitlab.denx.de/u-boot/custodians/u-boot-efi Pull request for UEFI sub-system for v2019.10-rc1 (2) * Implement the EVT_SIGNAL_VIRTUAL_ADDRESS_CHANGE event. * Address errors of type -Werror=address-of-packed-member when building with GCC9.1 * Fix an error when adding memory add addres 0x00000000. * Rework some code comments for Sphinx compliance.
# SPDX-License-Identifier: GPL-2.0+ # # Xilinx ZYNQ U-Boot # # (C) Copyright 2013 Xilinx, Inc. 1. About this This document describes the information about Xilinx Zynq U-Boot - like supported boards, ML status and TODO list. 2. Zynq boards Xilinx Zynq-7000 All Programmable SoCs enable extensive system level differentiation, integration, and flexibility through hardware, software, and I/O programmability. * zc702 (single qspi, gem0, mmc) [1] * zc706 (dual parallel qspi, gem0, mmc) [2] * zed (single qspi, gem0, mmc) [3] * microzed (single qspi, gem0, mmc) [4] * zc770 - zc770-xm010 (single qspi, gem0, mmc) - zc770-xm011 (8 or 16 bit nand) - zc770-xm012 (nor) - zc770-xm013 (dual parallel qspi, gem1) 3. Building ex. configure and build for zc702 board $ make zynq_zc702_config $ make 4. Bootmode Zynq has a facility to read the bootmode from the slcr bootmode register once user is setting through jumpers on the board - see page no:1546 on [5] All possible bootmode values are defined in Table 6-2:Boot_Mode MIO Pins on [5]. board_late_init() will read the bootmode values using slcr bootmode register at runtime and assign the modeboot variable to specific bootmode string which is intern used in autoboot. SLCR bootmode register Bit[3:0] values #define ZYNQ_BM_NOR 0x02 #define ZYNQ_BM_SD 0x05 #define ZYNQ_BM_JTAG 0x0 "modeboot" variable can assign any of "norboot", "sdboot" or "jtagboot" bootmode strings at runtime. 5. Mainline status - Added basic board configurations support. - Added zynq u-boot bsp code - arch/arm/cpu/armv7/zynq - Added zynq boards named - zc70x, zed, microzed, zc770_xm010/xm011/xm012/xm013 - Added zynq drivers: serial - drivers/serial/serial_zynq.c net - drivers/net/zynq_gem.c mmc - drivers/mmc/zynq_sdhci.c spi - drivers/spi/zynq_spi.c qspi - drivers/spi/zynq_qspi.c i2c - drivers/i2c/zynq_i2c.c nand - drivers/mtd/nand/raw/zynq_nand.c - Done proper cleanups on board configurations - Added basic FDT support for zynq boards - d-cache support for zynq_gem.c 6. TODO - Add FDT support on individual drivers [1] http://www.xilinx.com/products/boards-and-kits/EK-Z7-ZC702-G.htm [2] http://www.xilinx.com/products/boards-and-kits/EK-Z7-ZC706-G.htm [3] http://zedboard.org/product/zedboard [4] http://zedboard.org/product/microzed [5] http://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf -- Jagannadha Sutradharudu Teki <jaganna@xilinx.com> Sun Dec 15 14:52:41 IST 2013