Jonas Karlman 9af0c7732b pci: pcie_dw_rockchip: Configure number of lanes and link width speed
Set number of lanes and link width speed control register based on the
num-lanes property.

Code imported almost 1:1 from dw_pcie_setup in mainline linux.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-10-07 10:23:12 +08:00
..
2022-01-19 18:11:34 +01:00
2022-01-19 18:11:34 +01:00