Ley Foon Tan de77811589 arm: socfpga: Restructure clock manager driver ...

Restructure clock manager driver in the preparation to support A10.
Move the Gen5 specific code to _gen5 files.

- Change all uint32_t to u32 and change to use macro BIT(n) for bit shift.
- Check return value from wait_for_bit(). So change return type to int for
  cm_write_with_phase() and cm_basic_init().

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>

2017-05-18 11:33:16 +02:00

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mach

arm: socfpga: Restructure clock manager driver

2017-05-18 11:33:16 +02:00