Marek Vasut b979e35230 ARM: imx6: Adjust DDR DRAM settings on DHCOM i.MX6 PDK ...

The board uses T-topology for the four x16 DRAM chips, so remove
the write-leveling from the SPL as that is only usefly on fly-by
topology and can be harmful on T-topology. Also update the DRAM
timing with values from calibration on multiple boards.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>

2017-11-16 10:43:22 +01:00

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dh_imx6

ARM: imx6: Adjust DDR DRAM settings on DHCOM i.MX6 PDK

2017-11-16 10:43:22 +01:00