Zhichun Hua db14f11dfe armv8/fsl-lsch3: Fix TCR_EL3 for the final MMU setup.
When final MMU table is setup in DDR, TCR attributes must match
those of the memroy for cacheability and shareability.

Signed-off-by: Zhichun Hua <zhichun.hua@freescale.com>
Signed-off-by: York Sun <yorksun@freescale.com>
2015-07-20 11:44:40 -07:00
..
2015-04-10 14:22:23 +02:00
2015-05-28 08:18:24 -04:00