Shengzhou Liu d8e5163ad8 drivers/ddr/fsl: Update clk_adjust of sdram_clk_cntl ...

The clk_adjust is of SDRAM_CLK_CNTL[5:8] 4-bits on MPC85xx and P-series,
but is of SDRAM_CLK_CNTL[5:9] 5-bits on T-series and LS-series SoCs.
We should update it to adapt the case that clk_adjust is odd data.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

2016-06-03 14:06:35 -07:00

..

altera

ddr: altera: Repair DQ window centering code

2016-04-20 11:28:45 +02:00

fsl

drivers/ddr/fsl: Update clk_adjust of sdram_clk_cntl

2016-06-03 14:06:35 -07:00

marvell

arm: mvebu: a38x: Weed out floating point use

2016-05-20 11:01:00 +02:00

microchip

drivers: ddr: Add DDR2 SDRAM controller driver for Microchip PIC32.

2016-02-01 22:14:01 +01:00