Bin Meng 4a3efd71cd riscv: Fix alignment of RELA sections in the linker scripts ...

In current linker script both .efi_runtime_rel and .rela.dyn sections
are of RELA type whose entry size is either 12 (RV32) or 24 (RV64).
These two are arranged as a continuous region on purpose so that the
prelink-riscv executable can fix up the PIE addresses in one loop.

However there is an 'ALIGN(8)' between these 2 sections which might
cause a gap to be inserted between these 2 sections to satisfy the
alignment requirement on RV32. This would break the assumption of
the prelink process and generate an unbootable image.

Fixes: 9a6569a043d3 ("riscv: Update alignment for some sections in linker scripts")
Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Rick Chen <rick@andestech.com>

2023-06-27 10:09:51 +08:00

..

cpu

riscv: Fix alignment of RELA sections in the linker scripts

2023-06-27 10:09:51 +08:00

dts

riscv: dts: jh7110: Add initial StarFive VisionFive v2 board device tree

2023-04-20 20:45:08 +08:00

include/asm

riscv: Correct a comment in io.h

2023-04-20 20:45:08 +08:00

lib

riscv: semihosting: replace inline assembly with assembly file

2023-03-06 19:24:34 -05:00

config.mk

riscv: Support CONFIG_REMAKE_ELF

2023-04-20 20:45:08 +08:00

Kconfig

board: starfive: Add TARGET_STARFIVE_VISIONFIVE2 to Kconfig

2023-04-20 16:08:45 +08:00

Makefile

riscv: support building double-float modules

2022-10-20 15:22:21 +08:00