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e165b1d34c
The EDMA3 controller’s primary purpose is to service data transfers that you program between two memory-mapped slave endpoints on the device. Typical usage includes, but is not limited to the following: - Servicing software-driven paging transfers (e.g., transfers from external memory, such as SDRAM to internal device memory, such as DSP L2 SRAM) - Servicing event-driven peripherals, such as a serial port - Performing sorting or sub-frame extraction of various data structures - Offloading data transfers from the main device DSP(s) - See the device-specific data manual for specific peripherals that are accessible via the EDMA3 controller Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
385 lines
12 KiB
C
385 lines
12 KiB
C
/*
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* Enhanced Direct Memory Access (EDMA3) Controller
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*
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* (C) Copyright 2014
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* Texas Instruments Incorporated, <www.ti.com>
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*
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* Author: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <asm/io.h>
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#include <common.h>
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#include <asm/ti-common/ti-edma3.h>
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#define EDMA3_SL_BASE(slot) (0x4000 + ((slot) << 5))
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#define EDMA3_SL_MAX_NUM 512
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#define EDMA3_SLOPT_FIFO_WIDTH_MASK (0x7 << 8)
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#define EDMA3_QCHMAP(ch) 0x0200 + ((ch) << 2)
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#define EDMA3_CHMAP_PARSET_MASK 0x1ff
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#define EDMA3_CHMAP_PARSET_SHIFT 0x5
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#define EDMA3_CHMAP_TRIGWORD_SHIFT 0x2
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#define EDMA3_QEMCR 0x314
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#define EDMA3_IPR 0x1068
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#define EDMA3_IPRH 0x106c
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#define EDMA3_ICR 0x1070
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#define EDMA3_ICRH 0x1074
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#define EDMA3_QEECR 0x1088
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#define EDMA3_QEESR 0x108c
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#define EDMA3_QSECR 0x1094
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/**
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* qedma3_start - start qdma on a channel
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* @base: base address of edma
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* @cfg: pinter to struct edma3_channel_config where you can set
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* the slot number to associate with, the chnum, which corresponds
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* your quick channel number 0-7, complete code - transfer complete code
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* and trigger slot word - which has to correspond to the word number in
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* edma3_slot_layout struct for generating event.
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*
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*/
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void qedma3_start(u32 base, struct edma3_channel_config *cfg)
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{
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u32 qchmap;
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/* Clear the pending int bit */
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if (cfg->complete_code < 32)
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__raw_writel(1 << cfg->complete_code, base + EDMA3_ICR);
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else
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__raw_writel(1 << cfg->complete_code, base + EDMA3_ICRH);
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/* Map parameter set and trigger word 7 to quick channel */
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qchmap = ((EDMA3_CHMAP_PARSET_MASK & cfg->slot)
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<< EDMA3_CHMAP_PARSET_SHIFT) |
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(cfg->trigger_slot_word << EDMA3_CHMAP_TRIGWORD_SHIFT);
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__raw_writel(qchmap, base + EDMA3_QCHMAP(cfg->chnum));
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/* Clear missed event if set*/
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__raw_writel(1 << cfg->chnum, base + EDMA3_QSECR);
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__raw_writel(1 << cfg->chnum, base + EDMA3_QEMCR);
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/* Enable qdma channel event */
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__raw_writel(1 << cfg->chnum, base + EDMA3_QEESR);
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}
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/**
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* edma3_set_dest - set initial DMA destination address in parameter RAM slot
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* @base: base address of edma
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* @slot: parameter RAM slot being configured
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* @dst: physical address of destination (memory, controller FIFO, etc)
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* @addressMode: INCR, except in very rare cases
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* @width: ignored unless @addressMode is FIFO, else specifies the
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* width to use when addressing the fifo (e.g. W8BIT, W32BIT)
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*
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* Note that the destination address is modified during the DMA transfer
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* according to edma3_set_dest_index().
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*/
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void edma3_set_dest(u32 base, int slot, u32 dst, enum edma3_address_mode mode,
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enum edma3_fifo_width width)
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{
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u32 opt;
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struct edma3_slot_layout *rg;
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rg = (struct edma3_slot_layout *)(base + EDMA3_SL_BASE(slot));
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opt = __raw_readl(&rg->opt);
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if (mode == FIFO)
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opt = (opt & EDMA3_SLOPT_FIFO_WIDTH_MASK) |
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(EDMA3_SLOPT_DST_ADDR_CONST_MODE |
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EDMA3_SLOPT_FIFO_WIDTH_SET(width));
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else
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opt &= ~EDMA3_SLOPT_DST_ADDR_CONST_MODE;
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__raw_writel(opt, &rg->opt);
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__raw_writel(dst, &rg->dst);
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}
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/**
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* edma3_set_dest_index - configure DMA destination address indexing
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* @base: base address of edma
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* @slot: parameter RAM slot being configured
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* @bidx: byte offset between destination arrays in a frame
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* @cidx: byte offset between destination frames in a block
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*
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* Offsets are specified to support either contiguous or discontiguous
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* memory transfers, or repeated access to a hardware register, as needed.
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* When accessing hardware registers, both offsets are normally zero.
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*/
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void edma3_set_dest_index(u32 base, unsigned slot, int bidx, int cidx)
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{
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u32 src_dst_bidx;
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u32 src_dst_cidx;
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struct edma3_slot_layout *rg;
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rg = (struct edma3_slot_layout *)(base + EDMA3_SL_BASE(slot));
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src_dst_bidx = __raw_readl(&rg->src_dst_bidx);
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src_dst_cidx = __raw_readl(&rg->src_dst_cidx);
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__raw_writel((src_dst_bidx & 0x0000ffff) | (bidx << 16),
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&rg->src_dst_bidx);
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__raw_writel((src_dst_cidx & 0x0000ffff) | (cidx << 16),
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&rg->src_dst_cidx);
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}
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/**
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* edma3_set_dest_addr - set destination address for slot only
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*/
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void edma3_set_dest_addr(u32 base, int slot, u32 dst)
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{
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struct edma3_slot_layout *rg;
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rg = (struct edma3_slot_layout *)(base + EDMA3_SL_BASE(slot));
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__raw_writel(dst, &rg->dst);
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}
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/**
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* edma3_set_src - set initial DMA source address in parameter RAM slot
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* @base: base address of edma
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* @slot: parameter RAM slot being configured
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* @src_port: physical address of source (memory, controller FIFO, etc)
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* @mode: INCR, except in very rare cases
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* @width: ignored unless @addressMode is FIFO, else specifies the
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* width to use when addressing the fifo (e.g. W8BIT, W32BIT)
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*
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* Note that the source address is modified during the DMA transfer
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* according to edma3_set_src_index().
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*/
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void edma3_set_src(u32 base, int slot, u32 src, enum edma3_address_mode mode,
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enum edma3_fifo_width width)
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{
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u32 opt;
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struct edma3_slot_layout *rg;
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rg = (struct edma3_slot_layout *)(base + EDMA3_SL_BASE(slot));
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opt = __raw_readl(&rg->opt);
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if (mode == FIFO)
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opt = (opt & EDMA3_SLOPT_FIFO_WIDTH_MASK) |
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(EDMA3_SLOPT_DST_ADDR_CONST_MODE |
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EDMA3_SLOPT_FIFO_WIDTH_SET(width));
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else
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opt &= ~EDMA3_SLOPT_DST_ADDR_CONST_MODE;
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__raw_writel(opt, &rg->opt);
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__raw_writel(src, &rg->src);
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}
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/**
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* edma3_set_src_index - configure DMA source address indexing
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* @base: base address of edma
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* @slot: parameter RAM slot being configured
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* @bidx: byte offset between source arrays in a frame
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* @cidx: byte offset between source frames in a block
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*
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* Offsets are specified to support either contiguous or discontiguous
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* memory transfers, or repeated access to a hardware register, as needed.
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* When accessing hardware registers, both offsets are normally zero.
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*/
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void edma3_set_src_index(u32 base, unsigned slot, int bidx, int cidx)
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{
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u32 src_dst_bidx;
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u32 src_dst_cidx;
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struct edma3_slot_layout *rg;
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rg = (struct edma3_slot_layout *)(base + EDMA3_SL_BASE(slot));
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src_dst_bidx = __raw_readl(&rg->src_dst_bidx);
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src_dst_cidx = __raw_readl(&rg->src_dst_cidx);
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__raw_writel((src_dst_bidx & 0xffff0000) | bidx,
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&rg->src_dst_bidx);
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__raw_writel((src_dst_cidx & 0xffff0000) | cidx,
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&rg->src_dst_cidx);
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}
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/**
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* edma3_set_src_addr - set source address for slot only
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*/
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void edma3_set_src_addr(u32 base, int slot, u32 src)
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{
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struct edma3_slot_layout *rg;
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rg = (struct edma3_slot_layout *)(base + EDMA3_SL_BASE(slot));
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__raw_writel(src, &rg->src);
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}
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/**
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* edma3_set_transfer_params - configure DMA transfer parameters
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* @base: base address of edma
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* @slot: parameter RAM slot being configured
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* @acnt: how many bytes per array (at least one)
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* @bcnt: how many arrays per frame (at least one)
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* @ccnt: how many frames per block (at least one)
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* @bcnt_rld: used only for A-Synchronized transfers; this specifies
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* the value to reload into bcnt when it decrements to zero
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* @sync_mode: ASYNC or ABSYNC
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*
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* See the EDMA3 documentation to understand how to configure and link
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* transfers using the fields in PaRAM slots. If you are not doing it
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* all at once with edma3_write_slot(), you will use this routine
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* plus two calls each for source and destination, setting the initial
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* address and saying how to index that address.
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*
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* An example of an A-Synchronized transfer is a serial link using a
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* single word shift register. In that case, @acnt would be equal to
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* that word size; the serial controller issues a DMA synchronization
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* event to transfer each word, and memory access by the DMA transfer
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* controller will be word-at-a-time.
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*
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* An example of an AB-Synchronized transfer is a device using a FIFO.
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* In that case, @acnt equals the FIFO width and @bcnt equals its depth.
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* The controller with the FIFO issues DMA synchronization events when
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* the FIFO threshold is reached, and the DMA transfer controller will
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* transfer one frame to (or from) the FIFO. It will probably use
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* efficient burst modes to access memory.
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*/
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void edma3_set_transfer_params(u32 base, int slot, int acnt,
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int bcnt, int ccnt, u16 bcnt_rld,
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enum edma3_sync_dimension sync_mode)
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{
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u32 opt;
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u32 link_bcntrld;
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struct edma3_slot_layout *rg;
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rg = (struct edma3_slot_layout *)(base + EDMA3_SL_BASE(slot));
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link_bcntrld = __raw_readl(&rg->link_bcntrld);
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__raw_writel((bcnt_rld << 16) | (0x0000ffff & link_bcntrld),
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&rg->link_bcntrld);
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opt = __raw_readl(&rg->opt);
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if (sync_mode == ASYNC)
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__raw_writel(opt & ~EDMA3_SLOPT_AB_SYNC, &rg->opt);
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else
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__raw_writel(opt | EDMA3_SLOPT_AB_SYNC, &rg->opt);
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/* Set the acount, bcount, ccount registers */
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__raw_writel((bcnt << 16) | (acnt & 0xffff), &rg->a_b_cnt);
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__raw_writel(0xffff & ccnt, &rg->ccnt);
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}
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/**
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* edma3_write_slot - write parameter RAM data for slot
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* @base: base address of edma
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* @slot: number of parameter RAM slot being modified
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* @param: data to be written into parameter RAM slot
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*
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* Use this to assign all parameters of a transfer at once. This
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* allows more efficient setup of transfers than issuing multiple
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* calls to set up those parameters in small pieces, and provides
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* complete control over all transfer options.
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*/
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void edma3_write_slot(u32 base, int slot, struct edma3_slot_layout *param)
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{
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int i;
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u32 *p = (u32 *)param;
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u32 *addr = (u32 *)(base + EDMA3_SL_BASE(slot));
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for (i = 0; i < sizeof(struct edma3_slot_layout)/4; i += 4)
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__raw_writel(*p++, addr++);
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}
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/**
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* edma3_read_slot - read parameter RAM data from slot
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* @base: base address of edma
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* @slot: number of parameter RAM slot being copied
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* @param: where to store copy of parameter RAM data
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*
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* Use this to read data from a parameter RAM slot, perhaps to
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* save them as a template for later reuse.
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*/
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void edma3_read_slot(u32 base, int slot, struct edma3_slot_layout *param)
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{
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int i;
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u32 *p = (u32 *)param;
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u32 *addr = (u32 *)(base + EDMA3_SL_BASE(slot));
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for (i = 0; i < sizeof(struct edma3_slot_layout)/4; i += 4)
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*p++ = __raw_readl(addr++);
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}
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void edma3_slot_configure(u32 base, int slot, struct edma3_slot_config *cfg)
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{
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struct edma3_slot_layout *rg;
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rg = (struct edma3_slot_layout *)(base + EDMA3_SL_BASE(slot));
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__raw_writel(cfg->opt, &rg->opt);
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__raw_writel(cfg->src, &rg->src);
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__raw_writel((cfg->bcnt << 16) | (cfg->acnt & 0xffff), &rg->a_b_cnt);
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__raw_writel(cfg->dst, &rg->dst);
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__raw_writel((cfg->dst_bidx << 16) |
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(cfg->src_bidx & 0xffff), &rg->src_dst_bidx);
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__raw_writel((cfg->bcntrld << 16) |
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(cfg->link & 0xffff), &rg->link_bcntrld);
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__raw_writel((cfg->dst_cidx << 16) |
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(cfg->src_cidx & 0xffff), &rg->src_dst_cidx);
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__raw_writel(0xffff & cfg->ccnt, &rg->ccnt);
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}
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/**
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* edma3_check_for_transfer - check if transfer coplete by checking
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* interrupt pending bit. Clear interrupt pending bit if complete.
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* @base: base address of edma
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* @cfg: pinter to struct edma3_channel_config which was passed
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* to qedma3_start when you started qdma channel
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*
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* Return 0 if complete, 1 if not.
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*/
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int edma3_check_for_transfer(u32 base, struct edma3_channel_config *cfg)
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{
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u32 inum;
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u32 ipr_base;
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u32 icr_base;
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if (cfg->complete_code < 32) {
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ipr_base = base + EDMA3_IPR;
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icr_base = base + EDMA3_ICR;
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inum = 1 << cfg->complete_code;
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} else {
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ipr_base = base + EDMA3_IPRH;
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icr_base = base + EDMA3_ICRH;
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inum = 1 << (cfg->complete_code - 32);
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}
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/* check complete interrupt */
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if (!(__raw_readl(ipr_base) & inum))
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return 1;
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/* clean up the pending int bit */
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__raw_writel(inum, icr_base);
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return 0;
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}
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/**
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* qedma3_stop - stops dma on the channel passed
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* @base: base address of edma
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* @cfg: pinter to struct edma3_channel_config which was passed
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* to qedma3_start when you started qdma channel
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*/
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void qedma3_stop(u32 base, struct edma3_channel_config *cfg)
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{
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/* Disable qdma channel event */
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__raw_writel(1 << cfg->chnum, base + EDMA3_QEECR);
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/* clean up the interrupt indication */
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if (cfg->complete_code < 32)
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__raw_writel(1 << cfg->complete_code, base + EDMA3_ICR);
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else
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__raw_writel(1 << cfg->complete_code, base + EDMA3_ICRH);
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/* Clear missed event if set*/
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__raw_writel(1 << cfg->chnum, base + EDMA3_QSECR);
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__raw_writel(1 << cfg->chnum, base + EDMA3_QEMCR);
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/* Clear the channel map */
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__raw_writel(0, base + EDMA3_QCHMAP(cfg->chnum));
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}
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