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	The conversion from offsets to C structs lost a little padding in the DMA register map. Accessing endpoints other than ep0 with DMA would fail as the addresses wouldn't be adjusted correctly. Signed-off-by: Cliff Cai <cliff.cai@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
		
			
				
	
	
		
			100 lines
		
	
	
		
			1.7 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
			
		
		
	
	
			100 lines
		
	
	
		
			1.7 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
| /*
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|  * Blackfin MUSB HCD (Host Controller Driver) for u-boot
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|  *
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|  * Copyright (c) 2008-2009 Analog Devices Inc.
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|  *
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|  * Licensed under the GPL-2 or later.
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|  */
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| 
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| #ifndef __BLACKFIN_USB_H__
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| #define __BLACKFIN_USB_H__
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| 
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| #include <linux/types.h>
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| 
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| /* Every register is 32bit aligned, but only 16bits in size */
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| #define ureg(name) u16 name; u16 __pad_##name;
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| 
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| #define musb_regs musb_regs
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| struct musb_regs {
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| 	/* common registers */
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| 	ureg(faddr)
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| 	ureg(power)
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| 	ureg(intrtx)
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| 	ureg(intrrx)
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| 	ureg(intrtxe)
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| 	ureg(intrrxe)
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| 	ureg(intrusb)
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| 	ureg(intrusbe)
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| 	ureg(frame)
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| 	ureg(index)
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| 	ureg(testmode)
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| 	ureg(globintr)
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| 	ureg(global_ctl)
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| 	u32	reserved0[3];
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| 	/* indexed registers */
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| 	ureg(txmaxp)
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| 	ureg(txcsr)
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| 	ureg(rxmaxp)
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| 	ureg(rxcsr)
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| 	ureg(rxcount)
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| 	ureg(txtype)
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| 	ureg(txinterval)
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| 	ureg(rxtype)
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| 	ureg(rxinterval)
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| 	u32	reserved1;
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| 	ureg(txcount)
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| 	u32	reserved2[5];
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| 	/* fifo */
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| 	u16	fifox[32];
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| 	/* OTG, dynamic FIFO, version & vendor registers */
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| 	u32	reserved3[16];
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| 	ureg(devctl)
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| 	ureg(vbus_irq)
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| 	ureg(vbus_mask)
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| 	u32 reserved4[15];
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| 	ureg(linkinfo)
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| 	ureg(vplen)
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| 	ureg(hseof1)
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| 	ureg(fseof1)
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| 	ureg(lseof1)
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| 	u32 reserved5[41];
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| 	/* target address registers */
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| 	struct musb_tar_regs {
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| 		ureg(txmaxp)
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| 		ureg(txcsr)
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| 		ureg(rxmaxp)
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| 		ureg(rxcsr)
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| 		ureg(rxcount)
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| 		ureg(txtype)
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| 		ureg(txinternal)
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| 		ureg(rxtype)
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| 		ureg(rxinternal)
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| 		u32	reserved6;
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| 		ureg(txcount)
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| 		u32 reserved7[5];
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| 	} tar[8];
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| } __attribute__((packed));
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| 
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| struct bfin_musb_dma_regs {
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| 	ureg(interrupt);
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| 	ureg(control);
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| 	ureg(addr_low);
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| 	ureg(addr_high);
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| 	ureg(count_low);
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| 	ureg(count_high);
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| 	u32 reserved0[2];
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| };
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| 
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| #undef ureg
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| 
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| /* EP5-EP7 are the only ones with 1024 byte FIFOs which BULK really needs */
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| #define MUSB_BULK_EP 5
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| 
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| /* Blackfin FIFO's are static */
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| #define MUSB_NO_DYNAMIC_FIFO
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| 
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| /* No HUB support :( */
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| #define MUSB_NO_MULTIPOINT
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| 
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| #endif
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