mirror of
https://source.denx.de/u-boot/u-boot.git
synced 2025-08-31 11:31:27 +02:00
d13cd77068
This commit sychronizes the header file for FU740 PRCI clocks with the one from Linux 5.19. The constant values are the same, but all constant names are changed (most are just prefixed with FU740_). Signed-off-by: Icenowy Zheng <uwu@icenowy.me> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
110 lines
2.2 KiB
Plaintext
110 lines
2.2 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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/*
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* (C) Copyright 2020-2021 SiFive, Inc
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*/
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#include <dt-bindings/reset/sifive-fu740-prci.h>
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/ {
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cpus {
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assigned-clocks = <&prci FU740_PRCI_CLK_COREPLL>;
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assigned-clock-rates = <1200000000>;
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u-boot,dm-spl;
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cpu0: cpu@0 {
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clocks = <&prci FU740_PRCI_CLK_COREPLL>;
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u-boot,dm-spl;
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status = "okay";
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cpu0_intc: interrupt-controller {
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u-boot,dm-spl;
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};
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};
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cpu1: cpu@1 {
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clocks = <&prci FU740_PRCI_CLK_COREPLL>;
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u-boot,dm-spl;
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cpu1_intc: interrupt-controller {
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u-boot,dm-spl;
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};
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};
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cpu2: cpu@2 {
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clocks = <&prci FU740_PRCI_CLK_COREPLL>;
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u-boot,dm-spl;
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cpu2_intc: interrupt-controller {
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u-boot,dm-spl;
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};
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};
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cpu3: cpu@3 {
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clocks = <&prci FU740_PRCI_CLK_COREPLL>;
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u-boot,dm-spl;
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cpu3_intc: interrupt-controller {
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u-boot,dm-spl;
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};
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};
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cpu4: cpu@4 {
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clocks = <&prci FU740_PRCI_CLK_COREPLL>;
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u-boot,dm-spl;
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cpu4_intc: interrupt-controller {
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u-boot,dm-spl;
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};
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};
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};
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soc {
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u-boot,dm-spl;
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clint: clint@2000000 {
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compatible = "riscv,clint0";
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interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7
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&cpu1_intc 3 &cpu1_intc 7
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&cpu2_intc 3 &cpu2_intc 7
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&cpu3_intc 3 &cpu3_intc 7
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&cpu4_intc 3 &cpu4_intc 7>;
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reg = <0x0 0x2000000 0x0 0x10000>;
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u-boot,dm-spl;
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};
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prci: clock-controller@10000000 {
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#reset-cells = <1>;
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resets = <&prci PRCI_RST_DDR_CTRL_N>,
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<&prci PRCI_RST_DDR_AXI_N>,
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<&prci PRCI_RST_DDR_AHB_N>,
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<&prci PRCI_RST_DDR_PHY_N>,
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<&prci PRCI_RST_GEMGXL_N>,
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<&prci PRCI_RST_CLTX_N>;
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reset-names = "ddr_ctrl", "ddr_axi", "ddr_ahb",
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"ddr_phy", "gemgxl_reset", "cltx_reset";
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};
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dmc: dmc@100b0000 {
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compatible = "sifive,fu740-c000-ddr";
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reg = <0x0 0x100b0000 0x0 0x0800
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0x0 0x100b2000 0x0 0x2000
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0x0 0x100b8000 0x0 0x1000>;
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clocks = <&prci FU740_PRCI_CLK_DDRPLL>;
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clock-frequency = <933333324>;
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u-boot,dm-spl;
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};
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};
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};
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&prci {
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u-boot,dm-spl;
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};
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&uart0 {
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u-boot,dm-spl;
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};
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&spi0 {
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u-boot,dm-spl;
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};
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&i2c0 {
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u-boot,dm-spl;
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};
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ð0 {
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assigned-clocks = <&prci FU740_PRCI_CLK_GEMGXLPLL>;
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assigned-clock-rates = <125125000>;
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};
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&ccache {
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status = "okay";
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};
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