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16f4d36c7b
When booting from QSPI, the boot ROM appears to mux the QSPI pins, but it's not guaranteed to be setup when booting from eMMC. Fix this by explicitly configuring the pinmux. Signed-off-by: Adam Ford <aford173@gmail.com>
85 lines
1.2 KiB
Plaintext
85 lines
1.2 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright 2021 LogicPD dba Beacon EmbeddedWorks
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*/
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/ {
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aliases {
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spi0 = &rpc;
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};
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soc {
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u-boot,dm-pre-reloc;
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};
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};
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&cpg {
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u-boot,dm-pre-reloc;
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};
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&ehci0 {
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clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>, <&versaclock5 3>;
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};
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&ehci1 {
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clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>, <&versaclock5 3>;
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};
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&extal_clk {
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u-boot,dm-pre-reloc;
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};
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&extalr_clk {
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u-boot,dm-pre-reloc;
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};
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&pfc {
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qspi_pins: qspi {
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groups = "qspi_ctrl", "qspi_data4";
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function = "qspi";
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};
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};
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&prr {
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u-boot,dm-pre-reloc;
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};
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&rpc {
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compatible = "renesas,rcar-gen3-rpc";
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pinctrl-0 = <&qspi_pins>;
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pinctrl-names = "default";
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num-cs = <1>;
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spi-max-frequency = <40000000>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "okay";
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flash0: spi-flash@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0>;
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compatible = "spi-flash", "jedec,spi-nor";
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spi-max-frequency = <40000000>;
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spi-tx-bus-width = <1>;
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spi-rx-bus-width = <1>;
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};
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};
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&sdhi0 {
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/delete-property/ cd-gpios;
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sd-uhs-sdr12;
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sd-uhs-sdr25;
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sd-uhs-sdr104;
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max-frequency = <208000000>;
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};
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&sdhi2 {
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status = "disabled";
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};
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&sdhi3 {
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mmc-ddr-1_8v;
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mmc-hs200-1_8v;
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mmc-hs400-1_8v;
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};
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