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d678a59d2d
When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
124 lines
2.5 KiB
C
124 lines
2.5 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2002
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* Lineo, Inc. <www.lineo.com>
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* Bernhard Kuhn <bkuhn@lineo.com>
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*
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* (C) Copyright 2002
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* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
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* Marius Groeger <mgroeger@sysgo.de>
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*
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* (C) Copyright 2002
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* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
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* Alex Zuepke <azu@sysgo.de>
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*/
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#include <common.h>
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#include <init.h>
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#include <time.h>
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#include <asm/global_data.h>
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#include <linux/delay.h>
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#include <asm/io.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/at91_tc.h>
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#include <asm/arch/clk.h>
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DECLARE_GLOBAL_DATA_PTR;
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/* the number of clocks per CONFIG_SYS_HZ */
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#define TIMER_LOAD_VAL (CFG_SYS_HZ_CLOCK/CONFIG_SYS_HZ)
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int timer_init(void)
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{
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at91_tc_t *tc = (at91_tc_t *) ATMEL_BASE_TC;
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at91_periph_clk_enable(ATMEL_ID_TC0);
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writel(0, &tc->bcr);
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writel(AT91_TC_BMR_TC0XC0S_NONE | AT91_TC_BMR_TC1XC1S_NONE |
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AT91_TC_BMR_TC2XC2S_NONE , &tc->bmr);
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writel(AT91_TC_CCR_CLKDIS, &tc->tc[0].ccr);
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/* set to MCLK/2 and restart the timer
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when the value in TC_RC is reached */
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writel(AT91_TC_CMR_TCCLKS_CLOCK1 | AT91_TC_CMR_CPCTRG, &tc->tc[0].cmr);
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writel(0xFFFFFFFF, &tc->tc[0].idr); /* disable interrupts */
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writel(TIMER_LOAD_VAL, &tc->tc[0].rc);
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writel(AT91_TC_CCR_SWTRG | AT91_TC_CCR_CLKEN, &tc->tc[0].ccr);
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gd->arch.lastinc = 0;
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gd->arch.tbl = 0;
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return 0;
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}
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/*
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* timer without interrupts
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*/
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ulong get_timer_raw(void)
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{
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at91_tc_t *tc = (at91_tc_t *) ATMEL_BASE_TC;
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u32 now;
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now = readl(&tc->tc[0].cv) & 0x0000ffff;
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if (now >= gd->arch.lastinc) {
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/* normal mode */
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gd->arch.tbl += now - gd->arch.lastinc;
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} else {
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/* we have an overflow ... */
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gd->arch.tbl += now + TIMER_LOAD_VAL - gd->arch.lastinc;
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}
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gd->arch.lastinc = now;
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return gd->arch.tbl;
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}
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static ulong get_timer_masked(void)
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{
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return get_timer_raw()/TIMER_LOAD_VAL;
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}
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ulong get_timer(ulong base)
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{
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return get_timer_masked() - base;
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}
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void __udelay(unsigned long usec)
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{
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u32 tmo;
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u32 endtime;
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signed long diff;
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tmo = CFG_SYS_HZ_CLOCK / 1000;
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tmo *= usec;
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tmo /= 1000;
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endtime = get_timer_raw() + tmo;
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do {
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u32 now = get_timer_raw();
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diff = endtime - now;
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} while (diff >= 0);
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}
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/*
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* This function is derived from PowerPC code (read timebase as long long).
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* On ARM it just returns the timer value.
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*/
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unsigned long long get_ticks(void)
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{
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return get_timer(0);
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}
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/*
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* This function is derived from PowerPC code (timebase clock frequency).
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* On ARM it returns the number of timer ticks per second.
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*/
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ulong get_tbclk(void)
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{
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return CONFIG_SYS_HZ;
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}
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