Eugeniy Paltsev e80dac0ab8 ARC: clk: introduce HSDK CGU clock driver
Synopsys HSDK clock controller generates and supplies clocks to various
controllers and peripherals within the SoC.

Each clock has assigned identifier and client device tree nodes can use
this identifier to specify the clock which they consume. All available
clocks are defined as preprocessor macros in the
dt-bindings/clock/snps,hsdk-cgu.h header and can be used in device
tree sources.

Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2017-12-11 11:36:23 +03:00
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#
# Xilinx ZYNQ U-Boot
#
# (C) Copyright 2013 Xilinx, Inc.
#
# SPDX-License-Identifier:	GPL-2.0+
#

1. About this

This document describes the information about Xilinx Zynq U-Boot -
like supported boards, ML status and TODO list.

2. Zynq boards

Xilinx Zynq-7000 All Programmable SoCs enable extensive system level
differentiation, integration, and flexibility through hardware, software,
and I/O programmability.

* zc702 (single qspi, gem0, mmc) [1]
* zc706 (dual parallel qspi, gem0, mmc) [2]
* zed (single qspi, gem0, mmc) [3]
* microzed (single qspi, gem0, mmc) [4]
* zc770
  - zc770-xm010 (single qspi, gem0, mmc)
  - zc770-xm011 (8 or 16 bit nand)
  - zc770-xm012 (nor)
  - zc770-xm013 (dual parallel qspi, gem1)

3. Building

 ex. configure and build for zc702 board
   $ make zynq_zc702_config
   $ make

4. Bootmode

Zynq has a facility to read the bootmode from the slcr bootmode register
once user is setting through jumpers on the board - see page no:1546 on [5]

All possible bootmode values are defined in Table 6-2:Boot_Mode MIO Pins
on [5].

board_late_init() will read the bootmode values using slcr bootmode register
at runtime and assign the modeboot variable to specific bootmode string which
is intern used in autoboot.

SLCR bootmode register Bit[3:0] values
#define ZYNQ_BM_NOR		0x02
#define ZYNQ_BM_SD		0x05
#define ZYNQ_BM_JTAG		0x0

"modeboot" variable can assign any of "norboot", "sdboot" or "jtagboot"
bootmode strings at runtime.

5. Mainline status

- Added basic board configurations support.
- Added zynq u-boot bsp code - arch/arm/cpu/armv7/zynq
- Added zynq boards named - zc70x, zed, microzed, zc770_xm010, zc770_xm012, zc770_xm013
- Added zynq drivers:
  serial - drivers/serial/serial_zynq.c
  net - drivers/net/zynq_gem.c
  mmc - drivers/mmc/zynq_sdhci.c
  mmc - drivers/mmc/zynq_sdhci.c
  spi-  drivers/spi/zynq_spi.c
  i2c - drivers/i2c/zynq_i2c.c
- Done proper cleanups on board configurations
- Added basic FDT support for zynq boards
- d-cache support for zynq_gem.c

6. TODO

- Add zynq boards support - zc770_xm011
- Add zynq qspi controller driver
- Add zynq nand controller driver
- Add FDT support on individual drivers

[1] http://www.xilinx.com/products/boards-and-kits/EK-Z7-ZC702-G.htm
[2] http://www.xilinx.com/products/boards-and-kits/EK-Z7-ZC706-G.htm
[3] http://zedboard.org/product/zedboard
[4] http://zedboard.org/product/microzed
[5] http://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf

--
Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Sun Dec 15 14:52:41 IST 2013