u-boot

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History

Paul Burton cc4f36435f MIPS: Break out of cache loops for unimplemented caches

If we run on a CPU which doesn't implement a particular cache then we
would previously get stuck in an infinite loop, executing a cache op on
the first "line" of the missing cache & then incrementing the address by
0. This was being avoided for the L2 caches, but not for the L1s. Fix
this by generalising the check for a zero line size & avoiding the cache
op loop when this is the case.

Signed-off-by: Paul Burton <paul.burton@mips.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: u-boot@lists.denx.de

2017-11-28 21:59:30 +01:00

cpu

MIPS: Drop unused PTR_COUNT_SHIFT from u-boot.lds

2017-11-28 21:59:30 +01:00

dts

mips: bmips: fix BCM3380 periph clock frequency

2017-05-31 15:45:29 +02:00

include/asm

MIPS: Clear instruction hazards in flush_cache()

2017-11-28 21:59:30 +01:00

lib

MIPS: Break out of cache loops for unimplemented caches