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447d1bd05a
Add support for configuring DRAM controller on STM32MP13xx SoC. The DRAM controller is basically identical to the DWC controller on STM32MP15xx SoC, except the bus width is reduced from 32bit to 16bit and a few registers and bits are therefore not present. Handle the difference by factoring these parts out. Use IS_ENABLE() as much as possible to assure code which is not enabled on builds for a single SoC gets compiled out. Handle the different offset of RCC_DDRITFCR register and missing DDRC2 clock the same way. Signed-off-by: Marek Vasut <marek.vasut@mailbox.org>