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ceec18491c
Add definitions for the FSP signature and the FSP init phase. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
52 lines
1.4 KiB
C
52 lines
1.4 KiB
C
/* SPDX-License-Identifier: Intel */
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/*
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* Copyright (C) 2013, Intel Corporation
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* Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
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*/
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#ifndef _FSP_HEADER_H_
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#define _FSP_HEADER_H_
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#define FSP_HEADER_OFF 0x94 /* Fixed FSP header offset in the FSP image */
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struct __packed fsp_header {
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u32 sign; /* 'FSPH' */
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u32 hdr_len; /* header length */
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u8 reserved1[3];
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u8 hdr_rev; /* header rev */
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u32 img_rev; /* image rev */
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char img_id[8]; /* signature string */
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u32 img_size; /* image size */
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u32 img_base; /* image base */
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u32 img_attr; /* image attribute */
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u32 cfg_region_off; /* configuration region offset */
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u32 cfg_region_size; /* configuration region size */
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u32 api_num; /* number of API entries */
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u32 fsp_tempram_init; /* tempram_init offset */
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u32 fsp_init; /* fsp_init offset */
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u32 fsp_notify; /* fsp_notify offset */
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u32 fsp_mem_init; /* fsp_mem_init offset */
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u32 fsp_tempram_exit; /* fsp_tempram_exit offset */
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u32 fsp_silicon_init; /* fsp_silicon_init offset */
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};
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#define FSP_HEADER_REVISION_1 1
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#define FSP_HEADER_REVISION_2 2
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enum fsp_type {
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FSP_ATTR_COMP_TYPE_FSP_T = 1,
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FSP_ATTR_COMP_TYPE_FSP_M = 2,
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FSP_ATTR_COMP_TYPE_FSP_S = 3,
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};
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enum {
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FSP_ATTR_GRAPHICS_SUPPORT = 1 << 0,
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FSP_ATTR_COMP_TYPE_SHIFT = 28,
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FSP_ATTR_COMP_TYPE_MASK = 0xfU << FSP_ATTR_COMP_TYPE_SHIFT,
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};
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#define EFI_FSPH_SIGNATURE SIGNATURE_32('F', 'S', 'P', 'H')
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#endif
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