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aefdec5277
On px30-ringneck the FIT payload is located at sector 0x200 compared to the more Rockchip common sector 0x4000 offset: SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x200 Because FIT payload is located at sector 0x200 and the TPL+SPL is located at sector 64, the combined size of TPL+SPL cannot take up more than 224KiB: (0x200 - 64) x 512 = 0x38000 (224 KiB) Adjust SPL_PAD_TO to match the used 0x200 sector offset. While at it, update the px30-ringneck-u-boot.dtsi to remove the now unnecessary override of simple-bin:fit:offset since SPL_PAD_TO matches with the current formula. Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de>