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https://source.denx.de/u-boot/u-boot.git
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83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
147 lines
5.1 KiB
C
147 lines
5.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2016-2017 Intel Corporation
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*/
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#ifndef _RESET_MANAGER_ARRIA10_H_
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#define _RESET_MANAGER_ARRIA10_H_
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#include <dt-bindings/reset/altr,rst-mgr-a10.h>
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void socfpga_watchdog_disable(void);
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void socfpga_reset_deassert_noc_ddr_scheduler(void);
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int socfpga_is_wdt_in_reset(void);
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void socfpga_emac_manage_reset(ulong emacbase, u32 state);
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int socfpga_reset_deassert_bridges_handoff(void);
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void socfpga_reset_assert_fpga_connected_peripherals(void);
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void socfpga_reset_deassert_osc1wd0(void);
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void socfpga_reset_uart(int assert);
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int socfpga_bridges_reset(void);
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struct socfpga_reset_manager {
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u32 stat;
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u32 ramstat;
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u32 miscstat;
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u32 ctrl;
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u32 hdsken;
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u32 hdskreq;
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u32 hdskack;
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u32 counts;
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u32 mpumodrst;
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u32 per0modrst;
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u32 per1modrst;
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u32 brgmodrst;
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u32 sysmodrst;
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u32 coldmodrst;
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u32 nrstmodrst;
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u32 dbgmodrst;
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u32 mpuwarmmask;
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u32 per0warmmask;
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u32 per1warmmask;
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u32 brgwarmmask;
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u32 syswarmmask;
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u32 nrstwarmmask;
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u32 l3warmmask;
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u32 tststa;
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u32 tstscratch;
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u32 hdsktimeout;
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u32 hmcintr;
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u32 hmcintren;
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u32 hmcintrens;
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u32 hmcintrenr;
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u32 hmcgpout;
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u32 hmcgpin;
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};
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/*
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* SocFPGA Arria10 reset IDs, bank mapping is as follows:
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* 0 ... mpumodrst
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* 1 ... per0modrst
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* 2 ... per1modrst
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* 3 ... brgmodrst
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* 4 ... sysmodrst
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*/
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#define RSTMGR_EMAC0 RSTMGR_DEFINE(1, 0)
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#define RSTMGR_EMAC1 RSTMGR_DEFINE(1, 1)
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#define RSTMGR_EMAC2 RSTMGR_DEFINE(1, 2)
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#define RSTMGR_NAND RSTMGR_DEFINE(1, 5)
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#define RSTMGR_QSPI RSTMGR_DEFINE(1, 6)
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#define RSTMGR_SDMMC RSTMGR_DEFINE(1, 7)
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#define RSTMGR_DMA RSTMGR_DEFINE(1, 16)
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#define RSTMGR_SPIM0 RSTMGR_DEFINE(1, 17)
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#define RSTMGR_SPIM1 RSTMGR_DEFINE(1, 18)
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#define RSTMGR_L4WD0 RSTMGR_DEFINE(2, 0)
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#define RSTMGR_L4WD1 RSTMGR_DEFINE(2, 1)
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#define RSTMGR_L4SYSTIMER0 RSTMGR_DEFINE(2, 2)
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#define RSTMGR_L4SYSTIMER1 RSTMGR_DEFINE(2, 3)
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#define RSTMGR_SPTIMER0 RSTMGR_DEFINE(2, 4)
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#define RSTMGR_SPTIMER1 RSTMGR_DEFINE(2, 5)
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#define RSTMGR_UART0 RSTMGR_DEFINE(2, 16)
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#define RSTMGR_UART1 RSTMGR_DEFINE(2, 17)
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#define RSTMGR_DDRSCH RSTMGR_DEFINE(3, 6)
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#define ALT_RSTMGR_CTL_SWWARMRSTREQ_SET_MSK BIT(1)
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#define ALT_RSTMGR_PER0MODRST_EMAC0_SET_MSK BIT(0)
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#define ALT_RSTMGR_PER0MODRST_EMAC1_SET_MSK BIT(1)
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#define ALT_RSTMGR_PER0MODRST_EMAC2_SET_MSK BIT(2)
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#define ALT_RSTMGR_PER0MODRST_USB0_SET_MSK BIT(3)
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#define ALT_RSTMGR_PER0MODRST_USB1_SET_MSK BIT(4)
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#define ALT_RSTMGR_PER0MODRST_NAND_SET_MSK BIT(5)
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#define ALT_RSTMGR_PER0MODRST_QSPI_SET_MSK BIT(6)
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#define ALT_RSTMGR_PER0MODRST_SDMMC_SET_MSK BIT(7)
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#define ALT_RSTMGR_PER0MODRST_EMACECC0_SET_MSK BIT(8)
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#define ALT_RSTMGR_PER0MODRST_EMACECC1_SET_MSK BIT(9)
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#define ALT_RSTMGR_PER0MODRST_EMACECC2_SET_MSK BIT(10)
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#define ALT_RSTMGR_PER0MODRST_USBECC0_SET_MSK BIT(11)
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#define ALT_RSTMGR_PER0MODRST_USBECC1_SET_MSK BIT(12)
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#define ALT_RSTMGR_PER0MODRST_NANDECC_SET_MSK BIT(13)
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#define ALT_RSTMGR_PER0MODRST_QSPIECC_SET_MSK BIT(14)
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#define ALT_RSTMGR_PER0MODRST_SDMMCECC_SET_MSK BIT(15)
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#define ALT_RSTMGR_PER0MODRST_DMA_SET_MSK BIT(16)
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#define ALT_RSTMGR_PER0MODRST_SPIM0_SET_MSK BIT(17)
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#define ALT_RSTMGR_PER0MODRST_SPIM1_SET_MSK BIT(18)
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#define ALT_RSTMGR_PER0MODRST_SPIS0_SET_MSK BIT(19)
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#define ALT_RSTMGR_PER0MODRST_SPIS1_SET_MSK BIT(20)
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#define ALT_RSTMGR_PER0MODRST_DMAECC_SET_MSK BIT(21)
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#define ALT_RSTMGR_PER0MODRST_EMACPTP_SET_MSK BIT(22)
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#define ALT_RSTMGR_PER0MODRST_DMAIF0_SET_MSK BIT(24)
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#define ALT_RSTMGR_PER0MODRST_DMAIF1_SET_MSK BIT(25)
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#define ALT_RSTMGR_PER0MODRST_DMAIF2_SET_MSK BIT(26)
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#define ALT_RSTMGR_PER0MODRST_DMAIF3_SET_MSK BIT(27)
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#define ALT_RSTMGR_PER0MODRST_DMAIF4_SET_MSK BIT(28)
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#define ALT_RSTMGR_PER0MODRST_DMAIF5_SET_MSK BIT(29)
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#define ALT_RSTMGR_PER0MODRST_DMAIF6_SET_MSK BIT(30)
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#define ALT_RSTMGR_PER0MODRST_DMAIF7_SET_MSK BIT(31)
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#define ALT_RSTMGR_PER1MODRST_WD0_SET_MSK BIT(0)
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#define ALT_RSTMGR_PER1MODRST_WD1_SET_MSK BIT(1)
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#define ALT_RSTMGR_PER1MODRST_L4SYSTMR0_SET_MSK BIT(2)
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#define ALT_RSTMGR_PER1MODRST_L4SYSTMR1_SET_MSK BIT(3)
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#define ALT_RSTMGR_PER1MODRST_SPTMR0_SET_MSK BIT(4)
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#define ALT_RSTMGR_PER1MODRST_SPTMR1_SET_MSK BIT(5)
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#define ALT_RSTMGR_PER1MODRST_I2C0_SET_MSK BIT(8)
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#define ALT_RSTMGR_PER1MODRST_I2C1_SET_MSK BIT(9)
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#define ALT_RSTMGR_PER1MODRST_I2C2_SET_MSK BIT(10)
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#define ALT_RSTMGR_PER1MODRST_I2C3_SET_MSK BIT(11)
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#define ALT_RSTMGR_PER1MODRST_I2C4_SET_MSK BIT(12)
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#define ALT_RSTMGR_PER1MODRST_UART0_SET_MSK BIT(16)
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#define ALT_RSTMGR_PER1MODRST_UART1_SET_MSK BIT(17)
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#define ALT_RSTMGR_PER1MODRST_GPIO0_SET_MSK BIT(24)
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#define ALT_RSTMGR_PER1MODRST_GPIO1_SET_MSK BIT(25)
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#define ALT_RSTMGR_PER1MODRST_GPIO2_SET_MSK BIT(26)
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#define ALT_RSTMGR_BRGMODRST_H2F_SET_MSK BIT(0)
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#define ALT_RSTMGR_BRGMODRST_LWH2F_SET_MSK BIT(1)
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#define ALT_RSTMGR_BRGMODRST_F2H_SET_MSK BIT(2)
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#define ALT_RSTMGR_BRGMODRST_F2SSDRAM0_SET_MSK BIT(3)
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#define ALT_RSTMGR_BRGMODRST_F2SSDRAM1_SET_MSK BIT(4)
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#define ALT_RSTMGR_BRGMODRST_F2SSDRAM2_SET_MSK BIT(5)
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#define ALT_RSTMGR_BRGMODRST_DDRSCH_SET_MSK BIT(6)
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#define ALT_RSTMGR_HDSKEN_SDRSELFREFEN_SET_MSK BIT(0)
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#define ALT_RSTMGR_HDSKEN_FPGAMGRHSEN_SET_MSK BIT(1)
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#define ALT_RSTMGR_HDSKEN_FPGAHSEN_SET_MSK BIT(2)
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#define ALT_RSTMGR_HDSKEN_ETRSTALLEN_SET_MSK BIT(3)
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#endif /* _RESET_MANAGER_ARRIA10_H_ */
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