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160 lines
3.8 KiB
C
160 lines
3.8 KiB
C
/*
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* (C) Copyright 2002 ELTEC Elektronik AG
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* Frank Gottschling <fgottschling@eltec.de>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#if defined(CONFIG_SYS_L2_BAB7xx)
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#include <pci.h>
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#include <mpc106.h>
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#include <asm/processor.h>
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/* defines L2CR register for MPC750 */
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#define L2CR_E 0x80000000
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#define L2CR_256K 0x10000000
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#define L2CR_512K 0x20000000
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#define L2CR_1024K 0x30000000
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#define L2CR_I 0x00200000
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#define L2CR_SL 0x00008000
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#define L2CR_IP 0x00000001
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/*----------------------------------------------------------------------------*/
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static int dummy (int dummy)
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{
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return (dummy+1);
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}
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/*----------------------------------------------------------------------------*/
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int l2_cache_enable (int l2control)
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{
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if (l2control) /* BAB750 */
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{
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mtspr(SPRN_L2CR, l2control);
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mtspr(SPRN_L2CR, (l2control | L2CR_I));
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while (mfspr(SPRN_L2CR) & L2CR_IP)
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;
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mtspr(SPRN_L2CR, (l2control | L2CR_E));
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return (0);
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}
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else /* BAB740 */
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{
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int picr1, picr2, mask;
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int picr2CacheSize, cacheSize;
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int *d;
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int devbusfn;
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u32 reg32;
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devbusfn = pci_find_device(PCI_VENDOR_ID_MOTOROLA,
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PCI_DEVICE_ID_MOTOROLA_MPC106, 0);
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if (devbusfn == -1)
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return (-1);
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pci_read_config_dword (devbusfn, PCI_PICR2, ®32);
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reg32 &= ~PICR2_L2_EN;
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pci_write_config_dword (devbusfn, PCI_PICR2, reg32);
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/* cache size */
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if (*(volatile unsigned char *) (CONFIG_SYS_ISA_IO + 0x220) & 0x04)
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{
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/* cache size is 512 KB */
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picr2CacheSize = PICR2_L2_SIZE_512K;
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cacheSize = 0x80000;
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}
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else
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{
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/* cache size is 256 KB */
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picr2CacheSize = PICR2_L2_SIZE_256K;
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cacheSize = 0x40000;
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}
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/* setup PICR1 */
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mask =
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~(PICR1_CF_BREAD_WS(1) |
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PICR1_CF_BREAD_WS(2) |
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PICR1_CF_CBA(0xff) |
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PICR1_CF_CACHE_1G |
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PICR1_CF_DPARK |
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PICR1_CF_APARK |
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PICR1_CF_L2_CACHE_MASK);
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picr1 =
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(PICR1_CF_CBA(0x3f) |
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PICR1_CF_CACHE_1G |
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PICR1_CF_APARK |
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PICR1_CF_DPARK |
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PICR1_CF_L2_COPY_BACK); /* PICR1_CF_L2_WRITE_THROUGH */
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pci_read_config_dword (devbusfn, PCI_PICR1, ®32);
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reg32 &= mask;
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reg32 |= picr1;
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pci_write_config_dword (devbusfn, PCI_PICR1, reg32);
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/*
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* invalidate all L2 cache
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*/
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picr2 =
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(PICR2_CF_INV_MODE |
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PICR2_CF_HIT_HIGH |
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PICR2_CF_MOD_HIGH |
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PICR2_CF_L2_HIT_DELAY(1) |
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PICR2_CF_APHASE_WS(1) |
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picr2CacheSize);
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pci_write_config_dword (devbusfn, PCI_PICR2, picr2);
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/*
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* dummy transactions
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*/
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for (d=0; d<(int *)(2*cacheSize); d++)
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dummy(*d);
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pci_write_config_dword (devbusfn, PCI_PICR2,
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(picr2 | PICR2_CF_FLUSH_L2));
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/* setup PICR2 */
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picr2 =
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(PICR2_CF_FAST_CASTOUT |
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PICR2_CF_WDATA |
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PICR2_CF_ADDR_ONLY_DISABLE |
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PICR2_CF_HIT_HIGH |
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PICR2_CF_MOD_HIGH |
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PICR2_L2_UPDATE_EN |
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PICR2_L2_EN |
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PICR2_CF_APHASE_WS(1) |
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PICR2_CF_DATA_RAM_PBURST |
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PICR2_CF_L2_HIT_DELAY(1) |
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PICR2_CF_SNOOP_WS(2) |
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picr2CacheSize);
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pci_write_config_dword (devbusfn, PCI_PICR2, picr2);
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}
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return (0);
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}
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/*----------------------------------------------------------------------------*/
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#endif /* (CONFIG_SYS_L2_BAB7xx) */
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