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253531bbd9
This driver implements the HW WATCHDOG functions. Which needs to set CONFIG_HW_WATCHDOG to use them. This is disabled by default for mx7ulp. Use watchdog for reset cpu. Implement this in the driver. Need to define CONFIG_ULP_WATCHDOG to build it. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
99 lines
2.1 KiB
C
99 lines
2.1 KiB
C
/*
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* Copyright (C) 2016 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/imx-regs.h>
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/*
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* MX7ULP WDOG Register Map
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*/
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struct wdog_regs {
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u8 cs1;
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u8 cs2;
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u16 reserve0;
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u32 cnt;
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u32 toval;
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u32 win;
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};
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#ifndef CONFIG_WATCHDOG_TIMEOUT_MSECS
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#define CONFIG_WATCHDOG_TIMEOUT_MSECS 0x1500
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#endif
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#define REFRESH_WORD0 0xA602 /* 1st refresh word */
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#define REFRESH_WORD1 0xB480 /* 2nd refresh word */
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#define UNLOCK_WORD0 0xC520 /* 1st unlock word */
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#define UNLOCK_WORD1 0xD928 /* 2nd unlock word */
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#define WDGCS1_WDGE (1<<7)
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#define WDGCS1_WDGUPDATE (1<<5)
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#define WDGCS2_FLG (1<<6)
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#define WDG_BUS_CLK (0x0)
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#define WDG_LPO_CLK (0x1)
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#define WDG_32KHZ_CLK (0x2)
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#define WDG_EXT_CLK (0x3)
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DECLARE_GLOBAL_DATA_PTR;
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void hw_watchdog_set_timeout(u16 val)
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{
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/* setting timeout value */
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struct wdog_regs *wdog = (struct wdog_regs *)WDOG_BASE_ADDR;
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writel(val, &wdog->toval);
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}
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void hw_watchdog_reset(void)
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{
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struct wdog_regs *wdog = (struct wdog_regs *)WDOG_BASE_ADDR;
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writel(REFRESH_WORD0, &wdog->cnt);
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writel(REFRESH_WORD1, &wdog->cnt);
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}
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void hw_watchdog_init(void)
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{
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u8 val;
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struct wdog_regs *wdog = (struct wdog_regs *)WDOG_BASE_ADDR;
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writel(UNLOCK_WORD0, &wdog->cnt);
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writel(UNLOCK_WORD1, &wdog->cnt);
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val = readb(&wdog->cs2);
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val |= WDGCS2_FLG;
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writeb(val, &wdog->cs2);
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hw_watchdog_set_timeout(CONFIG_WATCHDOG_TIMEOUT_MSECS);
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writel(0, &wdog->win);
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writeb(WDG_LPO_CLK, &wdog->cs2);/* setting 1-kHz clock source */
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writeb((WDGCS1_WDGE | WDGCS1_WDGUPDATE), &wdog->cs1);/* enable counter running */
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hw_watchdog_reset();
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}
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void reset_cpu(ulong addr)
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{
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struct wdog_regs *wdog = (struct wdog_regs *)WDOG_BASE_ADDR;
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writel(UNLOCK_WORD0, &wdog->cnt);
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writel(UNLOCK_WORD1, &wdog->cnt);
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hw_watchdog_set_timeout(5); /* 5ms timeout */
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writel(0, &wdog->win);
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writeb(WDG_LPO_CLK, &wdog->cs2);/* setting 1-kHz clock source */
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writeb(WDGCS1_WDGE, &wdog->cs1);/* enable counter running */
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hw_watchdog_reset();
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while (1);
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}
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