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cc7debc719
By default the legacy segments C/D/E/F do not decode to system RAM. Turn on the decode via Programmable Attribute Map (PAM) registers so that we can write configuration tables in the F segment. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
92 lines
2.4 KiB
C
92 lines
2.4 KiB
C
/*
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* Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <pci.h>
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#include <pci_rom.h>
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#include <asm/pci.h>
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#include <asm/arch/qemu.h>
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DECLARE_GLOBAL_DATA_PTR;
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void board_pci_setup_hose(struct pci_controller *hose)
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{
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hose->first_busno = 0;
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hose->last_busno = 0;
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/* PCI memory space */
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pci_set_region(hose->regions + 0,
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CONFIG_PCI_MEM_BUS,
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CONFIG_PCI_MEM_PHYS,
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CONFIG_PCI_MEM_SIZE,
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PCI_REGION_MEM);
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/* PCI IO space */
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pci_set_region(hose->regions + 1,
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CONFIG_PCI_IO_BUS,
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CONFIG_PCI_IO_PHYS,
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CONFIG_PCI_IO_SIZE,
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PCI_REGION_IO);
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pci_set_region(hose->regions + 2,
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CONFIG_PCI_PREF_BUS,
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CONFIG_PCI_PREF_PHYS,
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CONFIG_PCI_PREF_SIZE,
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PCI_REGION_PREFETCH);
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pci_set_region(hose->regions + 3,
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0,
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0,
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gd->ram_size,
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PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
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hose->region_count = 4;
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}
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int board_pci_post_scan(struct pci_controller *hose)
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{
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int ret = 0;
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ulong start;
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pci_dev_t bdf;
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struct pci_device_id graphic_card[] = { { 0x1234, 0x1111 } };
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u16 device;
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int pam, i;
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/*
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* QEMU emulated graphic card shows in the PCI configuration space with
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* PCI vendor id and device id as an artificial pair 0x1234:0x1111.
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* It is on PCI bus 0, function 0, but device number is not consistent
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* for the two x86 targets it supports. For i440FX and PIIX chipset
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* board, it shows as device 2, while for Q35 and ICH9 chipset board,
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* it shows as device 1. Here we locate its bdf at run-time based on
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* its vendor id and device id pair so we can support both boards.
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*/
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bdf = pci_find_devices(graphic_card, 0);
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if (bdf != -1) {
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start = get_timer(0);
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ret = pci_run_vga_bios(bdf, NULL, PCI_ROM_USE_NATIVE);
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debug("BIOS ran in %lums\n", get_timer(start));
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}
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/*
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* i440FX and Q35 chipset have different PAM register offset, but with
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* the same bitfield layout. Here we determine the offset based on its
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* PCI device ID.
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*/
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device = x86_pci_read_config16(PCI_BDF(0, 0, 0), PCI_DEVICE_ID);
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pam = (device == PCI_DEVICE_ID_INTEL_82441) ? I440FX_PAM : Q35_PAM;
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/*
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* Initialize Programmable Attribute Map (PAM) Registers
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*
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* Configure legacy segments C/D/E/F to system RAM
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*/
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for (i = 0; i < PAM_NUM; i++)
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x86_pci_write_config8(PCI_BDF(0, 0, 0), pam + i, PAM_RW);
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return ret;
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}
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