mirror of
https://source.denx.de/u-boot/u-boot.git
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157 lines
3.5 KiB
C
157 lines
3.5 KiB
C
/*
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* Copyright 2008 Freescale Semiconductor, Inc.
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*
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* (C) Copyright 2000
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/processor.h>
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#include <asm/mmu.h>
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void set_tlb(u8 tlb, u32 epn, u64 rpn,
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u8 perms, u8 wimge,
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u8 ts, u8 esel, u8 tsize, u8 iprot)
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{
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u32 _mas0, _mas1, _mas2, _mas3, _mas7;
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_mas0 = FSL_BOOKE_MAS0(tlb, esel, 0);
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_mas1 = FSL_BOOKE_MAS1(1, iprot, 0, ts, tsize);
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_mas2 = FSL_BOOKE_MAS2(epn, wimge);
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_mas3 = FSL_BOOKE_MAS3(rpn, 0, perms);
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_mas7 = rpn >> 32;
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mtspr(MAS0, _mas0);
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mtspr(MAS1, _mas1);
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mtspr(MAS2, _mas2);
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mtspr(MAS3, _mas3);
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#ifdef CONFIG_ENABLE_36BIT_PHYS
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mtspr(MAS7, _mas7);
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#endif
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asm volatile("isync;msync;tlbwe;isync");
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}
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void disable_tlb(u8 esel)
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{
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u32 _mas0, _mas1, _mas2, _mas3, _mas7;
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_mas0 = FSL_BOOKE_MAS0(1, esel, 0);
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_mas1 = 0;
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_mas2 = 0;
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_mas3 = 0;
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_mas7 = 0;
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mtspr(MAS0, _mas0);
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mtspr(MAS1, _mas1);
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mtspr(MAS2, _mas2);
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mtspr(MAS3, _mas3);
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#ifdef CONFIG_ENABLE_36BIT_PHYS
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mtspr(MAS7, _mas7);
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#endif
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asm volatile("isync;msync;tlbwe;isync");
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}
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void invalidate_tlb(u8 tlb)
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{
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if (tlb == 0)
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mtspr(MMUCSR0, 0x4);
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if (tlb == 1)
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mtspr(MMUCSR0, 0x2);
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}
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void init_tlbs(void)
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{
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int i;
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for (i = 0; i < num_tlb_entries; i++) {
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set_tlb(tlb_table[i].tlb, tlb_table[i].epn, tlb_table[i].rpn,
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tlb_table[i].perms, tlb_table[i].wimge,
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tlb_table[i].ts, tlb_table[i].esel, tlb_table[i].tsize,
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tlb_table[i].iprot);
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}
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return ;
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}
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unsigned int setup_ddr_tlbs(unsigned int memsize_in_meg)
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{
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unsigned int tlb_size;
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unsigned int ram_tlb_index;
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unsigned int ram_tlb_address;
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/*
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* Determine size of each TLB1 entry.
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*/
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switch (memsize_in_meg) {
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case 16:
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case 32:
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tlb_size = BOOKE_PAGESZ_16M;
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break;
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case 64:
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case 128:
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tlb_size = BOOKE_PAGESZ_64M;
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break;
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case 256:
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case 512:
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tlb_size = BOOKE_PAGESZ_256M;
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break;
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case 1024:
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case 2048:
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if (PVR_VER(get_pvr()) > PVR_VER(PVR_85xx))
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tlb_size = BOOKE_PAGESZ_1G;
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else
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tlb_size = BOOKE_PAGESZ_256M;
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break;
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default:
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puts("DDR: only 16M, 32M, 64M, 128M, 256M, 512M, 1G"
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" and 2G are supported.\n");
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/*
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* The memory was not able to be mapped.
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* Default to a small size.
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*/
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tlb_size = BOOKE_PAGESZ_64M;
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memsize_in_meg = 64;
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break;
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}
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/*
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* Configure DDR TLB1 entries.
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* Starting at TLB1 8, use no more than 8 TLB1 entries.
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*/
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ram_tlb_index = 8;
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ram_tlb_address = (unsigned int)CONFIG_SYS_DDR_SDRAM_BASE;
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while (ram_tlb_address < (memsize_in_meg * 1024 * 1024)
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&& ram_tlb_index < 16) {
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set_tlb(1, ram_tlb_address, ram_tlb_address,
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MAS3_SX|MAS3_SW|MAS3_SR, 0,
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0, ram_tlb_index, tlb_size, 1);
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ram_tlb_address += (0x1000 << ((tlb_size - 1) * 2));
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ram_tlb_index++;
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}
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/*
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* Confirm that the requested amount of memory was mapped.
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*/
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return memsize_in_meg;
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}
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