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This patch adds reset controller bits definition header file for MediaTek MT7621 SoC Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
39 lines
827 B
C
39 lines
827 B
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2022 MediaTek Inc. All rights reserved.
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*
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* Author: Weijie Gao <weijie.gao@mediatek.com>
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*/
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#ifndef _DT_BINDINGS_MT7621_RESET_H_
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#define _DT_BINDINGS_MT7621_RESET_H_
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#define RST_PPE 31
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#define RST_SDXC 30
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#define RST_CRYPTO 29
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#define RST_AUX_STCK 28
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#define RST_PCIE2 26
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#define RST_PCIE1 25
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#define RST_PCIE0 24
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#define RST_GMAC 23
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#define RST_UART3 21
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#define RST_UART2 20
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#define RST_UART1 19
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#define RST_SPI 18
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#define RST_I2S 17
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#define RST_I2C 16
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#define RST_NFI 15
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#define RST_GDMA 14
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#define RST_PIO 13
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#define RST_PCM 11
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#define RST_MC 10
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#define RST_INTC 9
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#define RST_TIMER 8
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#define RST_SPDIFTX 7
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#define RST_FE 6
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#define RST_HSDMA 5
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#define RST_MCM 2
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#define RST_SYS 0
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#endif /* _DT_BINDINGS_MT7621_RESET_H_ */
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