T Karthik Reddy ca0c0e07ad fpga: zynqpl: Flush dcache only for non-bitstream data
In case of aes decryption destination address range must be flushed
before transferring decrypted data to destination.

Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-06-24 13:07:58 +02:00
..
2020-05-18 21:19:18 -04:00
2020-05-18 21:19:18 -04:00
2020-05-18 21:19:18 -04:00