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d382025dc5
The Qualcom ETHQOS hardware supports an RGMII macro which needs to be configured according to following link speeds: - SPEED_1000 - SPEED_100 - SPEED_10 So add a corresponding glue driver to configure RGMII macro. Signed-off-by: Sumit Garg <sumit.garg@linaro.org> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
292 lines
9.3 KiB
C
292 lines
9.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright 2022 NXP
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*/
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#include <phy_interface.h>
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#include <linux/bitops.h>
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/* Core registers */
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#define EQOS_MAC_REGS_BASE 0x000
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struct eqos_mac_regs {
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u32 configuration; /* 0x000 */
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u32 unused_004[(0x070 - 0x004) / 4]; /* 0x004 */
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u32 q0_tx_flow_ctrl; /* 0x070 */
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u32 unused_070[(0x090 - 0x074) / 4]; /* 0x074 */
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u32 rx_flow_ctrl; /* 0x090 */
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u32 unused_094; /* 0x094 */
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u32 txq_prty_map0; /* 0x098 */
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u32 unused_09c; /* 0x09c */
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u32 rxq_ctrl0; /* 0x0a0 */
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u32 unused_0a4; /* 0x0a4 */
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u32 rxq_ctrl2; /* 0x0a8 */
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u32 unused_0ac[(0x0dc - 0x0ac) / 4]; /* 0x0ac */
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u32 us_tic_counter; /* 0x0dc */
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u32 unused_0e0[(0x11c - 0x0e0) / 4]; /* 0x0e0 */
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u32 hw_feature0; /* 0x11c */
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u32 hw_feature1; /* 0x120 */
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u32 hw_feature2; /* 0x124 */
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u32 unused_128[(0x200 - 0x128) / 4]; /* 0x128 */
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u32 mdio_address; /* 0x200 */
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u32 mdio_data; /* 0x204 */
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u32 unused_208[(0x300 - 0x208) / 4]; /* 0x208 */
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u32 address0_high; /* 0x300 */
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u32 address0_low; /* 0x304 */
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};
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#define EQOS_MAC_CONFIGURATION_GPSLCE BIT(23)
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#define EQOS_MAC_CONFIGURATION_CST BIT(21)
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#define EQOS_MAC_CONFIGURATION_ACS BIT(20)
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#define EQOS_MAC_CONFIGURATION_WD BIT(19)
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#define EQOS_MAC_CONFIGURATION_JD BIT(17)
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#define EQOS_MAC_CONFIGURATION_JE BIT(16)
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#define EQOS_MAC_CONFIGURATION_PS BIT(15)
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#define EQOS_MAC_CONFIGURATION_FES BIT(14)
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#define EQOS_MAC_CONFIGURATION_DM BIT(13)
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#define EQOS_MAC_CONFIGURATION_LM BIT(12)
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#define EQOS_MAC_CONFIGURATION_TE BIT(1)
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#define EQOS_MAC_CONFIGURATION_RE BIT(0)
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#define EQOS_MAC_Q0_TX_FLOW_CTRL_PT_SHIFT 16
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#define EQOS_MAC_Q0_TX_FLOW_CTRL_PT_MASK 0xffff
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#define EQOS_MAC_Q0_TX_FLOW_CTRL_TFE BIT(1)
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#define EQOS_MAC_RX_FLOW_CTRL_RFE BIT(0)
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#define EQOS_MAC_TXQ_PRTY_MAP0_PSTQ0_SHIFT 0
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#define EQOS_MAC_TXQ_PRTY_MAP0_PSTQ0_MASK 0xff
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#define EQOS_MAC_RXQ_CTRL0_RXQ0EN_SHIFT 0
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#define EQOS_MAC_RXQ_CTRL0_RXQ0EN_MASK 3
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#define EQOS_MAC_RXQ_CTRL0_RXQ0EN_NOT_ENABLED 0
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#define EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_DCB 2
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#define EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_AV 1
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#define EQOS_MAC_RXQ_CTRL2_PSRQ0_SHIFT 0
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#define EQOS_MAC_RXQ_CTRL2_PSRQ0_MASK 0xff
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#define EQOS_MAC_HW_FEATURE0_MMCSEL_SHIFT 8
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#define EQOS_MAC_HW_FEATURE0_HDSEL_SHIFT 2
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#define EQOS_MAC_HW_FEATURE0_GMIISEL_SHIFT 1
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#define EQOS_MAC_HW_FEATURE0_MIISEL_SHIFT 0
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#define EQOS_MAC_HW_FEATURE1_TXFIFOSIZE_SHIFT 6
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#define EQOS_MAC_HW_FEATURE1_TXFIFOSIZE_MASK 0x1f
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#define EQOS_MAC_HW_FEATURE1_RXFIFOSIZE_SHIFT 0
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#define EQOS_MAC_HW_FEATURE1_RXFIFOSIZE_MASK 0x1f
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#define EQOS_MAC_HW_FEATURE3_ASP_SHIFT 28
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#define EQOS_MAC_HW_FEATURE3_ASP_MASK 0x3
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#define EQOS_MAC_MDIO_ADDRESS_PA_SHIFT 21
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#define EQOS_MAC_MDIO_ADDRESS_RDA_SHIFT 16
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#define EQOS_MAC_MDIO_ADDRESS_CR_SHIFT 8
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#define EQOS_MAC_MDIO_ADDRESS_CR_20_35 2
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#define EQOS_MAC_MDIO_ADDRESS_CR_250_300 5
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#define EQOS_MAC_MDIO_ADDRESS_SKAP BIT(4)
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#define EQOS_MAC_MDIO_ADDRESS_GOC_SHIFT 2
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#define EQOS_MAC_MDIO_ADDRESS_GOC_READ 3
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#define EQOS_MAC_MDIO_ADDRESS_GOC_WRITE 1
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#define EQOS_MAC_MDIO_ADDRESS_C45E BIT(1)
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#define EQOS_MAC_MDIO_ADDRESS_GB BIT(0)
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#define EQOS_MAC_MDIO_DATA_GD_MASK 0xffff
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#define EQOS_MTL_REGS_BASE 0xd00
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struct eqos_mtl_regs {
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u32 txq0_operation_mode; /* 0xd00 */
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u32 unused_d04; /* 0xd04 */
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u32 txq0_debug; /* 0xd08 */
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u32 unused_d0c[(0xd18 - 0xd0c) / 4]; /* 0xd0c */
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u32 txq0_quantum_weight; /* 0xd18 */
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u32 unused_d1c[(0xd30 - 0xd1c) / 4]; /* 0xd1c */
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u32 rxq0_operation_mode; /* 0xd30 */
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u32 unused_d34; /* 0xd34 */
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u32 rxq0_debug; /* 0xd38 */
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};
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#define EQOS_MTL_TXQ0_OPERATION_MODE_TQS_SHIFT 16
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#define EQOS_MTL_TXQ0_OPERATION_MODE_TQS_MASK 0x1ff
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#define EQOS_MTL_TXQ0_OPERATION_MODE_TXQEN_SHIFT 2
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#define EQOS_MTL_TXQ0_OPERATION_MODE_TXQEN_MASK 3
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#define EQOS_MTL_TXQ0_OPERATION_MODE_TXQEN_ENABLED 2
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#define EQOS_MTL_TXQ0_OPERATION_MODE_TSF BIT(1)
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#define EQOS_MTL_TXQ0_OPERATION_MODE_FTQ BIT(0)
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#define EQOS_MTL_TXQ0_DEBUG_TXQSTS BIT(4)
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#define EQOS_MTL_TXQ0_DEBUG_TRCSTS_SHIFT 1
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#define EQOS_MTL_TXQ0_DEBUG_TRCSTS_MASK 3
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#define EQOS_MTL_RXQ0_OPERATION_MODE_RQS_SHIFT 20
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#define EQOS_MTL_RXQ0_OPERATION_MODE_RQS_MASK 0x3ff
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#define EQOS_MTL_RXQ0_OPERATION_MODE_RFD_SHIFT 14
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#define EQOS_MTL_RXQ0_OPERATION_MODE_RFD_MASK 0x3f
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#define EQOS_MTL_RXQ0_OPERATION_MODE_RFA_SHIFT 8
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#define EQOS_MTL_RXQ0_OPERATION_MODE_RFA_MASK 0x3f
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#define EQOS_MTL_RXQ0_OPERATION_MODE_EHFC BIT(7)
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#define EQOS_MTL_RXQ0_OPERATION_MODE_RSF BIT(5)
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#define EQOS_MTL_RXQ0_DEBUG_PRXQ_SHIFT 16
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#define EQOS_MTL_RXQ0_DEBUG_PRXQ_MASK 0x7fff
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#define EQOS_MTL_RXQ0_DEBUG_RXQSTS_SHIFT 4
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#define EQOS_MTL_RXQ0_DEBUG_RXQSTS_MASK 3
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#define EQOS_DMA_REGS_BASE 0x1000
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struct eqos_dma_regs {
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u32 mode; /* 0x1000 */
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u32 sysbus_mode; /* 0x1004 */
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u32 unused_1008[(0x1100 - 0x1008) / 4]; /* 0x1008 */
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u32 ch0_control; /* 0x1100 */
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u32 ch0_tx_control; /* 0x1104 */
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u32 ch0_rx_control; /* 0x1108 */
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u32 unused_110c; /* 0x110c */
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u32 ch0_txdesc_list_haddress; /* 0x1110 */
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u32 ch0_txdesc_list_address; /* 0x1114 */
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u32 ch0_rxdesc_list_haddress; /* 0x1118 */
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u32 ch0_rxdesc_list_address; /* 0x111c */
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u32 ch0_txdesc_tail_pointer; /* 0x1120 */
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u32 unused_1124; /* 0x1124 */
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u32 ch0_rxdesc_tail_pointer; /* 0x1128 */
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u32 ch0_txdesc_ring_length; /* 0x112c */
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u32 ch0_rxdesc_ring_length; /* 0x1130 */
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};
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#define EQOS_DMA_MODE_SWR BIT(0)
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#define EQOS_DMA_SYSBUS_MODE_RD_OSR_LMT_SHIFT 16
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#define EQOS_DMA_SYSBUS_MODE_RD_OSR_LMT_MASK 0xf
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#define EQOS_DMA_SYSBUS_MODE_EAME BIT(11)
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#define EQOS_DMA_SYSBUS_MODE_BLEN16 BIT(3)
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#define EQOS_DMA_SYSBUS_MODE_BLEN8 BIT(2)
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#define EQOS_DMA_SYSBUS_MODE_BLEN4 BIT(1)
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#define EQOS_DMA_CH0_CONTROL_DSL_SHIFT 18
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#define EQOS_DMA_CH0_CONTROL_DSL_MASK 0x7
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#define EQOS_DMA_CH0_CONTROL_PBLX8 BIT(16)
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#define EQOS_DMA_CH0_TX_CONTROL_TXPBL_SHIFT 16
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#define EQOS_DMA_CH0_TX_CONTROL_TXPBL_MASK 0x3f
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#define EQOS_DMA_CH0_TX_CONTROL_OSP BIT(4)
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#define EQOS_DMA_CH0_TX_CONTROL_ST BIT(0)
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#define EQOS_DMA_CH0_RX_CONTROL_RXPBL_SHIFT 16
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#define EQOS_DMA_CH0_RX_CONTROL_RXPBL_MASK 0x3f
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#define EQOS_DMA_CH0_RX_CONTROL_RBSZ_SHIFT 1
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#define EQOS_DMA_CH0_RX_CONTROL_RBSZ_MASK 0x3fff
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#define EQOS_DMA_CH0_RX_CONTROL_SR BIT(0)
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/* These registers are Tegra186-specific */
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#define EQOS_TEGRA186_REGS_BASE 0x8800
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struct eqos_tegra186_regs {
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u32 sdmemcomppadctrl; /* 0x8800 */
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u32 auto_cal_config; /* 0x8804 */
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u32 unused_8808; /* 0x8808 */
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u32 auto_cal_status; /* 0x880c */
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};
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#define EQOS_SDMEMCOMPPADCTRL_PAD_E_INPUT_OR_E_PWRD BIT(31)
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#define EQOS_AUTO_CAL_CONFIG_START BIT(31)
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#define EQOS_AUTO_CAL_CONFIG_ENABLE BIT(29)
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#define EQOS_AUTO_CAL_STATUS_ACTIVE BIT(31)
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/* Descriptors */
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#define EQOS_DESCRIPTORS_TX 4
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#define EQOS_DESCRIPTORS_RX 4
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#define EQOS_DESCRIPTORS_NUM (EQOS_DESCRIPTORS_TX + EQOS_DESCRIPTORS_RX)
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#define EQOS_BUFFER_ALIGN ARCH_DMA_MINALIGN
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#define EQOS_MAX_PACKET_SIZE ALIGN(1568, ARCH_DMA_MINALIGN)
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#define EQOS_RX_BUFFER_SIZE (EQOS_DESCRIPTORS_RX * EQOS_MAX_PACKET_SIZE)
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struct eqos_desc {
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u32 des0;
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u32 des1;
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u32 des2;
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u32 des3;
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};
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#define EQOS_DESC3_OWN BIT(31)
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#define EQOS_DESC3_FD BIT(29)
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#define EQOS_DESC3_LD BIT(28)
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#define EQOS_DESC3_BUF1V BIT(24)
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#define EQOS_AXI_WIDTH_32 4
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#define EQOS_AXI_WIDTH_64 8
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#define EQOS_AXI_WIDTH_128 16
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struct eqos_config {
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bool reg_access_always_ok;
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int mdio_wait;
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int swr_wait;
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int config_mac;
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int config_mac_mdio;
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unsigned int axi_bus_width;
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phy_interface_t (*interface)(const struct udevice *dev);
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struct eqos_ops *ops;
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};
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struct eqos_ops {
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void (*eqos_inval_desc)(void *desc);
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void (*eqos_flush_desc)(void *desc);
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void (*eqos_inval_buffer)(void *buf, size_t size);
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void (*eqos_flush_buffer)(void *buf, size_t size);
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int (*eqos_probe_resources)(struct udevice *dev);
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int (*eqos_remove_resources)(struct udevice *dev);
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int (*eqos_stop_resets)(struct udevice *dev);
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int (*eqos_start_resets)(struct udevice *dev);
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int (*eqos_stop_clks)(struct udevice *dev);
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int (*eqos_start_clks)(struct udevice *dev);
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int (*eqos_calibrate_pads)(struct udevice *dev);
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int (*eqos_disable_calibration)(struct udevice *dev);
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int (*eqos_set_tx_clk_speed)(struct udevice *dev);
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int (*eqos_get_enetaddr)(struct udevice *dev);
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ulong (*eqos_get_tick_clk_rate)(struct udevice *dev);
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};
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struct eqos_priv {
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struct udevice *dev;
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const struct eqos_config *config;
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fdt_addr_t regs;
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struct eqos_mac_regs *mac_regs;
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struct eqos_mtl_regs *mtl_regs;
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struct eqos_dma_regs *dma_regs;
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struct eqos_tegra186_regs *tegra186_regs;
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void *eqos_qcom_rgmii_regs;
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struct reset_ctl reset_ctl;
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struct gpio_desc phy_reset_gpio;
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struct clk clk_master_bus;
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struct clk clk_rx;
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struct clk clk_ptp_ref;
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struct clk clk_tx;
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struct clk clk_ck;
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struct clk clk_slave_bus;
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struct mii_dev *mii;
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struct phy_device *phy;
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ofnode phy_of_node;
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u32 max_speed;
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void *tx_descs;
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void *rx_descs;
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int tx_desc_idx, rx_desc_idx;
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unsigned int desc_size;
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unsigned int desc_per_cacheline;
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void *tx_dma_buf;
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void *rx_dma_buf;
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void *rx_pkt;
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bool started;
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bool reg_access_ok;
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bool clk_ck_enabled;
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unsigned int tx_fifo_sz, rx_fifo_sz;
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u32 reset_delays[3];
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};
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void eqos_inval_desc_generic(void *desc);
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void eqos_flush_desc_generic(void *desc);
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void eqos_inval_buffer_generic(void *buf, size_t size);
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void eqos_flush_buffer_generic(void *buf, size_t size);
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int eqos_null_ops(struct udevice *dev);
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extern struct eqos_config eqos_imx_config;
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extern struct eqos_config eqos_qcom_config;
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