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d0748898d8
This converts the following to Kconfig: CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS CONFIG_SYS_FSL_OTHER_DDR_NUM_CTRLS And we remove the entries from the README for a number of already converted items. Signed-off-by: Tom Rini <trini@konsulko.com>
345 lines
6.8 KiB
Plaintext
345 lines
6.8 KiB
Plaintext
config SYS_FSL_DDR
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bool
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help
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Select Freescale General DDR driver, shared between most Freescale
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PowerPC- based SoCs (such as mpc83xx, mpc85xx and ARM- based
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Layerscape SoCs (such as ls2080a).
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config SYS_FSL_MMDC
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bool
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help
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Select Freescale Multi Mode DDR controller (MMDC).
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config SYS_FSL_DDR_EMU
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bool
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help
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Specify emulator support for DDR. Some DDR features such as deskew
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training are not available.
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if SYS_FSL_DDR || SYS_FSL_MMDC
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config SYS_FSL_DDR_BE
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bool
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help
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Access DDR registers in big-endian
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config SYS_FSL_DDR_LE
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bool
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help
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Access DDR registers in little-endian
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config FSL_DDR_BIST
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bool
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config FSL_DDR_INTERACTIVE
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bool
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config FSL_DDR_SYNC_REFRESH
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bool
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config FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
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bool
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config SYS_FSL_OTHER_DDR_NUM_CTRLS
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bool
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menu "Freescale DDR controllers"
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depends on SYS_FSL_DDR
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config SYS_NUM_DDR_CTLRS
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int "Maximum DDR controllers"
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default 3 if ARCH_LS2080A || \
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ARCH_T4240
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default 2 if ARCH_B4860 || \
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ARCH_BSC9132 || \
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ARCH_P4080 || \
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ARCH_P5040 || \
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ARCH_LX2160A || \
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ARCH_LX2162A
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default 1
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config CHIP_SELECTS_PER_CTRL
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int "Number of chip selects per controller"
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default 4
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config DIMM_SLOTS_PER_CTLR
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int "Number of DIMM slots per controller"
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default 1
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config SYS_FSL_DDR_MAIN_NUM_CTRLS
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int "Number of controllers used as main memory"
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default SYS_NUM_DDR_CTLRS
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config SYS_FSL_DDR_VER
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int
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default 50 if SYS_FSL_DDR_VER_50
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default 47 if SYS_FSL_DDR_VER_47
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default 46 if SYS_FSL_DDR_VER_46
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default 44 if SYS_FSL_DDR_VER_44
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config SYS_FSL_DDR_VER_50
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bool
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config SYS_FSL_DDR_VER_47
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bool
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config SYS_FSL_DDR_VER_46
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bool
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config SYS_FSL_DDR_VER_44
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bool
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config SYS_FSL_DDRC_GEN1
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bool
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help
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Enable Freescale DDR controller.
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config SYS_FSL_DDRC_GEN2
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bool
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depends on !MPC86xx
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help
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Enable Freescale DDR2 controller.
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config SYS_FSL_DDRC_GEN3
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bool
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depends on PPC
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help
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Enable Freescale DDR3 controller for PowerPC SoCs.
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config SYS_FSL_DDRC_ARM_GEN3
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bool
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depends on ARM
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help
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Enable Freescale DDR3 controller for ARM SoCs.
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config SYS_FSL_DDRC_GEN4
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bool
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help
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Enable Freescale DDR4 controller.
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config SYS_FSL_HAS_DDR4
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bool
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config SYS_FSL_HAS_DDR3
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bool
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config SYS_FSL_HAS_DDR2
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bool
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config SYS_FSL_HAS_DDR1
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bool
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choice
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prompt "DDR technology"
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default SYS_FSL_DDR4 if SYS_FSL_HAS_DDR4
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default SYS_FSL_DDR3 if SYS_FSL_HAS_DDR3
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default SYS_FSL_DDR2 if SYS_FSL_HAS_DDR2
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default SYS_FSL_DDR1 if SYS_FSL_HAS_DDR1
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config SYS_FSL_DDR4
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bool "Freescale DDR4 controller"
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depends on SYS_FSL_HAS_DDR4
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imply DDR_SPD
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select SYS_FSL_DDRC_GEN4
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config SYS_FSL_DDR3
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bool "Freescale DDR3 controller"
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depends on SYS_FSL_HAS_DDR3
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imply DDR_SPD
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select SYS_FSL_DDRC_GEN3 if PPC
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select SYS_FSL_DDRC_ARM_GEN3 if ARM
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config SYS_FSL_DDR2
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bool "Freescale DDR2 controller"
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depends on SYS_FSL_HAS_DDR2
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imply DDR_SPD
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select SYS_FSL_DDRC_GEN2 if (!MPC86xx && !SYS_FSL_DDRC_GEN3)
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config SYS_FSL_DDR1
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bool "Freescale DDR1 controller"
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depends on SYS_FSL_HAS_DDR1
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imply DDR_SPD
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select SYS_FSL_DDRC_GEN1
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endchoice
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endmenu
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config FSL_DMA
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def_bool y if DDR_ECC && MPC85xx && !ECC_INIT_VIA_DDRCONTROLLER
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config DDR_ECC
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bool "ECC DDR memory support"
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config DDR_ECC_CMD
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bool "Access the ECC features of the memory controller"
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depends on DDR_ECC && MPC83xx
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default y
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config ECC_INIT_VIA_DDRCONTROLLER
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bool "DDR Memory controller initializes memory."
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help
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Use the DDR controller to auto initialize memory. If not enabled,
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the DMA controller is responsible for doing this.
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config SYS_DDR_RAW_TIMING
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bool "Get DDR timing information from something other than SPD"
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help
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This is common with soldered DDR chips onboard without SPD. DDR raw
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timing parameters are extracted from datasheet and hard-coded into
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header files or board specific files.
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config SYS_FSL_DDR_INTLV_256B
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bool "Enforce 256-byte interleave"
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help
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DDR controller interleaving on 256-byte. This is a special
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interleaving mode, handled by Dickens for Freescale layerscape SoCs
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with ARM core.
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endif
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menu "PowerPC / M68K initial memory controller definitions (FLASH, SDRAM, etc)"
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depends on MCF52x2 || MPC8xx || MPC83xx || MPC85xx
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config SYS_BR0_PRELIM_BOOL
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bool "Define Bank 0"
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config SYS_BR0_PRELIM
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hex "Preliminary value for BR0"
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depends on SYS_BR0_PRELIM_BOOL
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config SYS_OR0_PRELIM
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hex "Preliminary value for OR0"
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depends on SYS_BR0_PRELIM_BOOL
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config SYS_BR1_PRELIM_BOOL
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bool "Define Bank 1"
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config SYS_BR1_PRELIM
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hex "Preliminary value for BR1"
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depends on SYS_BR1_PRELIM_BOOL
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config SYS_OR1_PRELIM
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hex "Preliminary value for OR1"
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depends on SYS_BR1_PRELIM_BOOL
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config SYS_BR2_PRELIM_BOOL
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bool "Define Bank 2"
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config SYS_BR2_PRELIM
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hex "Preliminary value for BR2"
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depends on SYS_BR2_PRELIM_BOOL
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config SYS_OR2_PRELIM
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hex "Preliminary value for OR2"
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depends on SYS_BR2_PRELIM_BOOL
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config SYS_BR3_PRELIM_BOOL
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bool "Define Bank 3"
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config SYS_BR3_PRELIM
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hex "Preliminary value for BR3"
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depends on SYS_BR3_PRELIM_BOOL
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config SYS_OR3_PRELIM
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hex "Preliminary value for OR3"
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depends on SYS_BR3_PRELIM_BOOL
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config SYS_BR4_PRELIM_BOOL
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bool "Define Bank 4"
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config SYS_BR4_PRELIM
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hex "Preliminary value for BR4"
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depends on SYS_BR4_PRELIM_BOOL
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config SYS_OR4_PRELIM
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hex "Preliminary value for OR4"
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depends on SYS_BR4_PRELIM_BOOL
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config SYS_BR5_PRELIM_BOOL
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bool "Define Bank 5"
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config SYS_BR5_PRELIM
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hex "Preliminary value for BR5"
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depends on SYS_BR5_PRELIM_BOOL
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config SYS_OR5_PRELIM
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hex "Preliminary value for OR5"
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depends on SYS_BR5_PRELIM_BOOL
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config SYS_BR6_PRELIM_BOOL
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bool "Define Bank 6"
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config SYS_BR6_PRELIM
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hex "Preliminary value for BR6"
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depends on SYS_BR6_PRELIM_BOOL
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config SYS_OR6_PRELIM
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hex "Preliminary value for OR6"
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depends on SYS_BR6_PRELIM_BOOL
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config SYS_BR7_PRELIM_BOOL
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bool "Define Bank 7"
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config SYS_BR7_PRELIM
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hex "Preliminary value for BR7"
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depends on SYS_BR7_PRELIM_BOOL
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config SYS_OR7_PRELIM
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hex "Preliminary value for OR7"
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depends on SYS_BR7_PRELIM_BOOL
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endmenu
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if TARGET_P1010RDB_PA || TARGET_P1010RDB_PB || TARGET_P1020RDB_PC || \
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TARGET_P1020RDB_PD || TARGET_P2020RDB
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config COMMON_INIT_DDR
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bool "Do not have a TLB entry to cover common DDR init with serial presence detect (SPD)"
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config SPL_COMMON_INIT_DDR
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bool "Do not have a TLB entry to cover common DDR init with SPD in SPL"
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config TPL_COMMON_INIT_DDR
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bool "Do not have a TLB entry to cover common DDR init with SPD in TPL"
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endif
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config SYS_FSL_ERRATUM_A008378
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bool
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config SYS_FSL_ERRATUM_A008109
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bool
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config SYS_FSL_ERRATUM_A008511
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bool
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config SYS_FSL_ERRATUM_A009663
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bool
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config SYS_FSL_ERRATUM_A009801
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bool
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config SYS_FSL_ERRATUM_A009803
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bool
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config SYS_FSL_ERRATUM_A009942
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bool
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config SYS_FSL_ERRATUM_A010165
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bool
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config SYS_FSL_ERRATUM_NMG_DDR120
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bool
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config SYS_FSL_ERRATUM_DDR_115
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bool
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config SYS_FSL_ERRATUM_DDR111_DDR134
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bool
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config SYS_FSL_ERRATUM_DDR_A003
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bool
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config SYS_FSL_ERRATUM_DDR_A003474
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bool
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