mirror of
https://source.denx.de/u-boot/u-boot.git
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280 lines
7.7 KiB
C
280 lines
7.7 KiB
C
/*
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* Copyright 2008, Freescale Semiconductor, Inc
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* Andy Fleming
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*
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* Based (loosely) on the Linux code
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef _MMC_H_
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#define _MMC_H_
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#include <linux/list.h>
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#define SD_VERSION_SD 0x20000
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#define SD_VERSION_2 (SD_VERSION_SD | 0x20)
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#define SD_VERSION_1_0 (SD_VERSION_SD | 0x10)
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#define SD_VERSION_1_10 (SD_VERSION_SD | 0x1a)
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#define MMC_VERSION_MMC 0x10000
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#define MMC_VERSION_UNKNOWN (MMC_VERSION_MMC)
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#define MMC_VERSION_1_2 (MMC_VERSION_MMC | 0x12)
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#define MMC_VERSION_1_4 (MMC_VERSION_MMC | 0x14)
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#define MMC_VERSION_2_2 (MMC_VERSION_MMC | 0x22)
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#define MMC_VERSION_3 (MMC_VERSION_MMC | 0x30)
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#define MMC_VERSION_4 (MMC_VERSION_MMC | 0x40)
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#define MMC_MODE_HS 0x001
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#define MMC_MODE_HS_52MHz 0x010
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#define MMC_MODE_4BIT 0x100
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#define MMC_MODE_8BIT 0x200
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#define SD_DATA_4BIT 0x00040000
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#define IS_SD(x) (x->version & SD_VERSION_SD)
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#define MMC_DATA_READ 1
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#define MMC_DATA_WRITE 2
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#define NO_CARD_ERR -16 /* No SD/MMC card inserted */
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#define UNUSABLE_ERR -17 /* Unusable Card */
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#define COMM_ERR -18 /* Communications Error */
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#define TIMEOUT -19
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#define MMC_CMD_GO_IDLE_STATE 0
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#define MMC_CMD_SEND_OP_COND 1
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#define MMC_CMD_ALL_SEND_CID 2
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#define MMC_CMD_SET_RELATIVE_ADDR 3
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#define MMC_CMD_SET_DSR 4
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#define MMC_CMD_SWITCH 6
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#define MMC_CMD_SELECT_CARD 7
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#define MMC_CMD_SEND_EXT_CSD 8
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#define MMC_CMD_SEND_CSD 9
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#define MMC_CMD_SEND_CID 10
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#define MMC_CMD_STOP_TRANSMISSION 12
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#define MMC_CMD_SEND_STATUS 13
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#define MMC_CMD_SET_BLOCKLEN 16
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#define MMC_CMD_READ_SINGLE_BLOCK 17
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#define MMC_CMD_READ_MULTIPLE_BLOCK 18
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#define MMC_CMD_WRITE_SINGLE_BLOCK 24
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#define MMC_CMD_WRITE_MULTIPLE_BLOCK 25
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#define MMC_CMD_APP_CMD 55
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#define SD_CMD_SEND_RELATIVE_ADDR 3
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#define SD_CMD_SWITCH_FUNC 6
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#define SD_CMD_SEND_IF_COND 8
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#define SD_CMD_APP_SET_BUS_WIDTH 6
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#define SD_CMD_APP_SEND_OP_COND 41
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#define SD_CMD_APP_SEND_SCR 51
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/* SCR definitions in different words */
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#define SD_HIGHSPEED_BUSY 0x00020000
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#define SD_HIGHSPEED_SUPPORTED 0x00020000
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#define MMC_HS_TIMING 0x00000100
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#define MMC_HS_52MHZ 0x2
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#define OCR_BUSY 0x80000000
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#define OCR_HCS 0x40000000
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#define MMC_VDD_165_195 0x00000080 /* VDD voltage 1.65 - 1.95 */
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#define MMC_VDD_20_21 0x00000100 /* VDD voltage 2.0 ~ 2.1 */
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#define MMC_VDD_21_22 0x00000200 /* VDD voltage 2.1 ~ 2.2 */
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#define MMC_VDD_22_23 0x00000400 /* VDD voltage 2.2 ~ 2.3 */
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#define MMC_VDD_23_24 0x00000800 /* VDD voltage 2.3 ~ 2.4 */
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#define MMC_VDD_24_25 0x00001000 /* VDD voltage 2.4 ~ 2.5 */
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#define MMC_VDD_25_26 0x00002000 /* VDD voltage 2.5 ~ 2.6 */
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#define MMC_VDD_26_27 0x00004000 /* VDD voltage 2.6 ~ 2.7 */
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#define MMC_VDD_27_28 0x00008000 /* VDD voltage 2.7 ~ 2.8 */
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#define MMC_VDD_28_29 0x00010000 /* VDD voltage 2.8 ~ 2.9 */
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#define MMC_VDD_29_30 0x00020000 /* VDD voltage 2.9 ~ 3.0 */
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#define MMC_VDD_30_31 0x00040000 /* VDD voltage 3.0 ~ 3.1 */
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#define MMC_VDD_31_32 0x00080000 /* VDD voltage 3.1 ~ 3.2 */
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#define MMC_VDD_32_33 0x00100000 /* VDD voltage 3.2 ~ 3.3 */
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#define MMC_VDD_33_34 0x00200000 /* VDD voltage 3.3 ~ 3.4 */
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#define MMC_VDD_34_35 0x00400000 /* VDD voltage 3.4 ~ 3.5 */
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#define MMC_VDD_35_36 0x00800000 /* VDD voltage 3.5 ~ 3.6 */
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#define MMC_SWITCH_MODE_CMD_SET 0x00 /* Change the command set */
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#define MMC_SWITCH_MODE_SET_BITS 0x01 /* Set bits in EXT_CSD byte
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addressed by index which are
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1 in value field */
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#define MMC_SWITCH_MODE_CLEAR_BITS 0x02 /* Clear bits in EXT_CSD byte
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addressed by index, which are
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1 in value field */
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#define MMC_SWITCH_MODE_WRITE_BYTE 0x03 /* Set target byte to value */
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#define SD_SWITCH_CHECK 0
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#define SD_SWITCH_SWITCH 1
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/*
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* EXT_CSD fields
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*/
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#define EXT_CSD_BUS_WIDTH 183 /* R/W */
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#define EXT_CSD_HS_TIMING 185 /* R/W */
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#define EXT_CSD_CARD_TYPE 196 /* RO */
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#define EXT_CSD_REV 192 /* RO */
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#define EXT_CSD_SEC_CNT 212 /* RO, 4 bytes */
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/*
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* EXT_CSD field definitions
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*/
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#define EXT_CSD_CMD_SET_NORMAL (1<<0)
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#define EXT_CSD_CMD_SET_SECURE (1<<1)
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#define EXT_CSD_CMD_SET_CPSECURE (1<<2)
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#define EXT_CSD_CARD_TYPE_26 (1<<0) /* Card can run at 26MHz */
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#define EXT_CSD_CARD_TYPE_52 (1<<1) /* Card can run at 52MHz */
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#define EXT_CSD_BUS_WIDTH_1 0 /* Card is in 1 bit mode */
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#define EXT_CSD_BUS_WIDTH_4 1 /* Card is in 4 bit mode */
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#define EXT_CSD_BUS_WIDTH_8 2 /* Card is in 8 bit mode */
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#define R1_ILLEGAL_COMMAND (1 << 22)
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#define R1_APP_CMD (1 << 5)
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#define MMC_RSP_PRESENT (1 << 0)
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#define MMC_RSP_136 (1 << 1) /* 136 bit response */
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#define MMC_RSP_CRC (1 << 2) /* expect valid crc */
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#define MMC_RSP_BUSY (1 << 3) /* card may send busy */
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#define MMC_RSP_OPCODE (1 << 4) /* response contains opcode */
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#define MMC_RSP_NONE (0)
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#define MMC_RSP_R1 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
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#define MMC_RSP_R1b (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE| \
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MMC_RSP_BUSY)
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#define MMC_RSP_R2 (MMC_RSP_PRESENT|MMC_RSP_136|MMC_RSP_CRC)
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#define MMC_RSP_R3 (MMC_RSP_PRESENT)
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#define MMC_RSP_R4 (MMC_RSP_PRESENT)
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#define MMC_RSP_R5 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
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#define MMC_RSP_R6 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
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#define MMC_RSP_R7 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
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struct mmc_cid {
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unsigned long psn;
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unsigned short oid;
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unsigned char mid;
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unsigned char prv;
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unsigned char mdt;
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char pnm[7];
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};
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struct mmc_csd
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{
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u8 csd_structure:2,
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spec_vers:4,
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rsvd1:2;
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u8 taac;
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u8 nsac;
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u8 tran_speed;
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u16 ccc:12,
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read_bl_len:4;
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u64 read_bl_partial:1,
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write_blk_misalign:1,
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read_blk_misalign:1,
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dsr_imp:1,
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rsvd2:2,
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c_size:12,
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vdd_r_curr_min:3,
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vdd_r_curr_max:3,
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vdd_w_curr_min:3,
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vdd_w_curr_max:3,
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c_size_mult:3,
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sector_size:5,
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erase_grp_size:5,
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wp_grp_size:5,
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wp_grp_enable:1,
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default_ecc:2,
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r2w_factor:3,
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write_bl_len:4,
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write_bl_partial:1,
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rsvd3:5;
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u8 file_format_grp:1,
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copy:1,
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perm_write_protect:1,
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tmp_write_protect:1,
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file_format:2,
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ecc:2;
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u8 crc:7;
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u8 one:1;
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};
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struct mmc_cmd {
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ushort cmdidx;
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uint resp_type;
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uint cmdarg;
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uint response[4];
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uint flags;
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};
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struct mmc_data {
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union {
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char *dest;
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const char *src; /* src buffers don't get written to */
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};
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uint flags;
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uint blocks;
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uint blocksize;
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};
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struct mmc {
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struct list_head link;
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char name[32];
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void *priv;
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uint voltages;
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uint version;
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uint f_min;
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uint f_max;
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int high_capacity;
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uint bus_width;
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uint clock;
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uint card_caps;
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uint host_caps;
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uint ocr;
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uint scr[2];
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uint csd[4];
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uint cid[4];
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ushort rca;
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uint tran_speed;
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uint read_bl_len;
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uint write_bl_len;
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u64 capacity;
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block_dev_desc_t block_dev;
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int (*send_cmd)(struct mmc *mmc,
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struct mmc_cmd *cmd, struct mmc_data *data);
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void (*set_ios)(struct mmc *mmc);
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int (*init)(struct mmc *mmc);
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};
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int mmc_register(struct mmc *mmc);
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int mmc_initialize(bd_t *bis);
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int mmc_init(struct mmc *mmc);
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int mmc_read(struct mmc *mmc, u64 src, uchar *dst, int size);
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struct mmc *find_mmc_device(int dev_num);
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void print_mmc_devices(char separator);
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#ifndef CONFIG_GENERIC_MMC
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int mmc_legacy_init(int verbose);
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#endif
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#endif /* _MMC_H_ */
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