Ang, Chee Hong
a03e9d9fe5
ARM: socfpga: stratix10: Disable FPGA2SOC reset
...
Software must never reset FPGA2SOC bridge. This bridge must only be
reset by POR/COLD/WARM reset. Asserting the FPGA2SOC reset by software
can cause the SoC to lock-up if there are traffics being drived into
FPGA2SOC bridge.
Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
2019-05-06 12:44:45 +02:00
..
2018-05-07 09:34:12 -04:00
2018-11-29 12:45:15 +01:00
2018-05-18 10:30:47 +02:00
2018-05-08 21:08:42 +02:00
2018-08-24 12:05:20 +02:00
2018-05-07 09:34:12 -04:00
2018-05-18 10:30:47 +02:00
2018-05-18 10:30:47 +02:00
2018-07-12 09:22:12 +02:00
2018-05-07 09:34:12 -04:00
2018-05-07 09:34:12 -04:00
2018-05-07 09:34:12 -04:00
2018-05-07 09:34:12 -04:00
2018-05-07 09:34:12 -04:00
2018-05-18 10:30:47 +02:00
2018-12-20 17:12:25 +01:00
2019-04-29 10:08:56 +02:00
2018-05-07 09:34:12 -04:00
2018-05-07 09:34:12 -04:00
2018-08-13 22:35:42 +02:00
2019-04-29 10:08:55 +02:00
2019-05-06 12:44:45 +02:00
2019-02-18 13:00:53 +01:00
2018-05-07 09:34:12 -04:00
2018-05-18 10:30:47 +02:00
2018-05-18 10:30:47 +02:00
2019-04-17 22:20:16 +02:00
2018-05-18 10:30:47 +02:00
2018-05-07 09:34:12 -04:00
2018-05-07 09:34:12 -04:00
2018-08-15 12:41:09 +02:00
2018-05-18 10:30:48 +02:00
2018-05-07 09:34:12 -04:00