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0f89860494
Use the standard lowercase "xx" capitalization that other Freescale architectures use for CPU defines to prevent confusion and errors Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
188 lines
5.6 KiB
Plaintext
188 lines
5.6 KiB
Plaintext
Freescale MPC8349E-mITX and MPC8349E-mITX-GP Boards
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---------------------------------------------------
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1. Board Description
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The MPC8349E-mITX and MPC8349E-mITX-GP are reference boards featuring
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the Freescale MPC8349E processor in a Mini-ITX form factor.
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The MPC8349E-mITX-GP is an MPC8349E-mITX with the following differences:
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A) One 8MB on-board flash EEPROM chip, instead of two.
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B) No SATA controller
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C) No Compact Flash slot
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D) No Mini-PCI slot
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E) No Vitesse 7385 5-port Ethernet switch
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F) No 4-port USB Type-A interface
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2. Board Switches and Jumpers
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2.0 Descriptions for all of the board jumpers can be found in the User
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Guide. Of particular interest to U-Boot developers is jumper J22:
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Pos. Name Default Description
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-----------------------------------------------------------------------
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A LGPL0 ON (0) HRCW source, bit 0
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B LGPL1 ON (0) HRCW source, bit 1
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C LGPL3 ON (0) HRCW source, bit 2
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D LGPL5 OFF (1) PCI_SYNC_OUT frequency
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E BOOT1 ON (0) Flash EEPROM boot device
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F PCI_M66EN ON (0) PCI 66MHz enable
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G I2C-WP ON (0) I2C EEPROM write protection
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H F_WP OFF (1) Flash EEPROM write protection
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Jumper J22.E is only for the ITX, and it decides the configuration
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of the flash chips. If J22.E is ON (i.e. jumpered), then flash chip
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U4 is located at address FE000000 and flash chip U7 is at FE800000.
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If J22.E is OFF, then U7 is at FE000000 and U4 is at FE800000.
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For U-Boot development, J22.E can be used to switch back-and-forth
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between two U-Boot images.
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3. Memory Map
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3.1. The memory map should look pretty much like this:
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0x0000_0000 - 0x0FFF_FFFF DDR SDRAM (256 MB)
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0x8000_0000 - 0x9FFF_FFFF PCI1 memory space (512 MB)
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0xA000_0000 - 0xBFFF_FFFF PCI2 memory space (512 MB)
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0xE000_0000 - 0xEFFF_FFFF IMMR (1 MB)
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0xE200_0000 - 0xE2FF_FFFF PCI1 I/O space (16 MB)
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0xE300_0000 - 0xE3FF_FFFF PCI2 I/O space (16 MB)
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0xF000_0000 - 0xF000_FFFF Compact Flash (ITX only)
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0xF001_0000 - 0xF001_FFFF Local bus expansion slot
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0xF800_0000 - 0xF801_FFFF Vitesse 7385 Parallel Interface (ITX only)
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0xFE00_0000 - 0xFE7F_FFFF First 8MB bank of Flash memory
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0xFE80_0000 - 0xFEFF_FFFF Second 8MB bank of Flash memory (ITX only)
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3.2 Flash EEPROM layout.
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On the ITX, jumper J22.E is used to determine which flash chips are
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at which address. When J22.E is switched, addresses from FE000000
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to FE7FFFFF are swapped with addresses from FE800000 to FEFFFFFF.
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On the ITX, at the normal boot address (aka HIGHBOOT):
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FE00_0000 HRCW
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FE70_0000 Alternative U-Boot image
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FE80_0000 Alternative HRCW
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FEF0_0000 U-Boot image
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FEFF_FFFF End of flash
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On the ITX, at the low boot address (LOWBOOT)
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FE00_0000 HRCW and U-Boot image
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FE04_0000 U-Boot environment variables
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FE80_0000 Alternative HRCW and U-Boot image
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FEFF_FFFF End of flash
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On the ITX-GP, the only option is LOWBOOT and there is only one chip
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FE00_0000 HRCW and U-Boot image
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FE04_0000 U-Boot environment variables
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F7FF_FFFF End of flash
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4. Definitions
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4.1 Explanation of NEW definitions in:
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include/configs/MPC8349ITX.h
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CONFIG_MPC83xx MPC83xx family
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CONFIG_MPC8349 MPC8349 specific
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CONFIG_MPC8349ITX MPC8349E-mITX
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CONFIG_MPC8349ITXGP MPC8349E-mITX-GP
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5. Compilation
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Assuming you're using BASH shell:
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export CROSS_COMPILE=your-cross-compile-prefix
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cd u-boot
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make distclean
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make MPC8349ITX_config
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or:
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make MPC8349ITXGP_config
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or:
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make MPC8349ITX_LOWBOOT_config
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make
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6. Downloading and Flashing Images
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6.1 Download via tftp:
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tftp $loadaddr <uboot>
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where "<uboot>" is the path and filename, on the TFTP server, of
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the U-Boot image.
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6.1 Reflash U-Boot Image using U-Boot
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setenv uboot <uboot>
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run tftpflash
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where "<uboot>" is the path and filename, on the TFTP server, of
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the U-Boot image.
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6.2 Using the HRCW to switch between two different U-Boot images on the ITX
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Because the ITX has 16MB of flash, it is possible to keep two U-Boot
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images in flash, and use the HRCW to specify which one is to be used
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when the board boots. This trick is especially effective with a
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hardware debugger that can override the HRCW, such as the BDI-2000.
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When the BMS bit in the HRCW is 0, the ITX will boot the U-Boot image
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at address FE000000. When the BMS bit is 1, the ITX will boot the
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image at address FEF00000.
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Therefore, just put a U-Boot image at both FE000000 and FEF00000 and
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change the BMS bit whenever you want to boot the other image.
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Step-by-step instructions:
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1) Build an ITX image to be loaded at FEF00000
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make distclean
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make MPC8349ITX_config
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make
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2) Take the u-boot.bin image and flash it at FEF00000.
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tftp $loadaddr u-boot.bin
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protect off all
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erase FEF00000 +$filesize
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cp.b $loadaddr FEF00000 $filesize
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3) Build an ITX image to be loaded at FE000000
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make distclean
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make MPC8349ITX_LOWBOOT_config
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make
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4) Take the u-boot.bin image and flash it at FE000000.
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tftp $loadaddr u-boot.bin
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protect off FE000000 +$filesize
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erase FE000000 +$filesize
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cp.b $loadaddr FE000000 $filesize
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The HRCW in flash is currently set to boot the image at FE000000.
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If you have a hardware debugger, configure it to set the HRCW to
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B460A000 04040000 if you want to boot the image at FEF00000, or set
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it to B060A000 04040000 if you want to boot the image at FE000000.
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To change the HRCW in flash to boot the image at FEF00000, use these
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U-Boot commands:
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cp.b FE000000 1000 10000 ; copy 1st flash sector to 1000
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mw.b 1020 b4 8 ; modify BMS bit
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protect off FE000000 +10000
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erase FE000000 +10000
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cp.b 1000 FE000000 10000
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7. Notes
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1) The console baudrate for MPC8349EITX is 115200bps.
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