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BCH8_ECC scheme implemented in omap_gpmc.c driver has following favours +-----------------------------------+-----------------+-----------------+ |ECC Scheme | ECC Calculation | Error Detection | +-----------------------------------+-----------------+-----------------+ |OMAP_ECC_BCH8_CODE_HW |GPMC |ELM H/W engine | |OMAP_ECC_BCH8_CODE_HW_DETECTION_SW |GPMC |S/W BCH library | +-----------------------------------+-----------------+-----------------+ Current implementation limits the BCH8_CODE_HW only for AM33xx device family. (using CONFIG_AM33XX). However, other SoC families (like TI81xx) also have ELM hardware module, and can support ECC error detection using ELM. This patch - removes CONFIG_AM33xx Thus this driver can be reused by all devices having ELM h/w engine. - adds omap_select_ecc_scheme() A common function to handle ecc-scheme related configurations. This can be used both during device-probe and via user-space u-boot commads to change ecc-scheme. During device probe ecc-scheme is selected based on CONFIG_NAND_OMAP_ELM or CONFIG_NAND_OMAP_BCH8 - enables CONFIG_BCH S/W library (lib/bch.c) required by OMAP_ECC_BCHx_CODE_HW_DETECTION_SW is enabled by CONFIG_BCH. - enables CONFIG_SYS_NAND_ONFI_DETECTION for auto-detection of ONFI compliant NAND devices - updates following README doc doc/README.nand board/ti/am335x/README doc/README.omap3 Signed-off-by: Pekon Gupta <pekon@ti.com> [scottwood@freescale.com: fixed unused variable warning] Signed-off-by: Scott Wood <scottwood@freescale.com>
88 lines
2.2 KiB
C
88 lines
2.2 KiB
C
/*
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* (C) Copyright 2004-2008 Texas Instruments, <www.ti.com>
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* Rohit Choraria <rohitkc@ti.com>
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*
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* (C) Copyright 2013 Andreas Bießmann <andreas.devel@googlemail.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __ASM_OMAP_GPMC_H
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#define __ASM_OMAP_GPMC_H
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#include <asm/arch/omap_gpmc.h>
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#define GPMC_BUF_EMPTY 0
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#define GPMC_BUF_FULL 1
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#define ECCCLEAR (0x1 << 8)
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#define ECCRESULTREG1 (0x1 << 0)
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#define ECCSIZE512BYTE 0xFF
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#define ECCSIZE1 (ECCSIZE512BYTE << 22)
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#define ECCSIZE0 (ECCSIZE512BYTE << 12)
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#define ECCSIZE0SEL (0x000 << 0)
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/* Generic ECC Layouts */
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/* Large Page x8 NAND device Layout */
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#ifdef GPMC_NAND_ECC_LP_x8_LAYOUT
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#define GPMC_NAND_HW_ECC_LAYOUT {\
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.eccbytes = 12,\
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.eccpos = {1, 2, 3, 4, 5, 6, 7, 8,\
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9, 10, 11, 12},\
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.oobfree = {\
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{.offset = 13,\
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.length = 51 } } \
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}
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#endif
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/* Large Page x16 NAND device Layout */
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#ifdef GPMC_NAND_ECC_LP_x16_LAYOUT
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#define GPMC_NAND_HW_ECC_LAYOUT {\
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.eccbytes = 12,\
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.eccpos = {2, 3, 4, 5, 6, 7, 8, 9,\
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10, 11, 12, 13},\
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.oobfree = {\
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{.offset = 14,\
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.length = 50 } } \
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}
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#endif
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/* Small Page x8 NAND device Layout */
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#ifdef GPMC_NAND_ECC_SP_x8_LAYOUT
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#define GPMC_NAND_HW_ECC_LAYOUT {\
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.eccbytes = 3,\
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.eccpos = {1, 2, 3},\
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.oobfree = {\
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{.offset = 4,\
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.length = 12 } } \
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}
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#endif
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/* Small Page x16 NAND device Layout */
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#ifdef GPMC_NAND_ECC_SP_x16_LAYOUT
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#define GPMC_NAND_HW_ECC_LAYOUT {\
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.eccbytes = 3,\
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.eccpos = {2, 3, 4},\
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.oobfree = {\
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{.offset = 5,\
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.length = 11 } } \
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}
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#endif
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enum omap_ecc {
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/* 1-bit ECC calculation by Software, Error detection by Software */
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OMAP_ECC_HAM1_CODE_SW = 1, /* avoid un-initialized int can be 0x0 */
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/* 1-bit ECC calculation by GPMC, Error detection by Software */
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/* ECC layout compatible to legacy ROMCODE. */
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OMAP_ECC_HAM1_CODE_HW,
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/* 4-bit ECC calculation by GPMC, Error detection by Software */
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OMAP_ECC_BCH4_CODE_HW_DETECTION_SW,
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/* 4-bit ECC calculation by GPMC, Error detection by ELM */
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OMAP_ECC_BCH4_CODE_HW,
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/* 8-bit ECC calculation by GPMC, Error detection by Software */
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OMAP_ECC_BCH8_CODE_HW_DETECTION_SW,
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/* 8-bit ECC calculation by GPMC, Error detection by ELM */
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OMAP_ECC_BCH8_CODE_HW,
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};
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#endif /* __ASM_OMAP_GPMC_H */
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