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1e501f9136
T4240 internal UTMI phy is different comparing to previous UTMI PHY in P3041. This patch adds USB 2.0 UTMI Dual PHY new memory map and enable it for T4240. The phy timing is very sensitive and moving the phy enable code to cpu_init.c will not work. Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
145 lines
4.1 KiB
C
145 lines
4.1 KiB
C
/*
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* (C) Copyright 2009, 2011 Freescale Semiconductor, Inc.
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*
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* (C) Copyright 2008, Excito Elektronik i Sk=E5ne AB
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*
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* Author: Tor Krill tor@excito.com
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <pci.h>
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#include <usb.h>
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#include <asm/io.h>
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#include <usb/ehci-fsl.h>
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#include <hwconfig.h>
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#include "ehci.h"
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/* Check USB PHY clock valid */
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static int usb_phy_clk_valid(struct usb_ehci *ehci)
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{
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if (!((in_be32(&ehci->control) & PHY_CLK_VALID) ||
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in_be32(&ehci->prictrl))) {
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printf("USB PHY clock invalid!\n");
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return 0;
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} else {
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return 1;
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}
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}
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/*
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* Create the appropriate control structures to manage
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* a new EHCI host controller.
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*
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* Excerpts from linux ehci fsl driver.
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*/
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int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor)
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{
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struct usb_ehci *ehci;
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const char *phy_type = NULL;
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size_t len;
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#ifdef CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
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char usb_phy[5];
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usb_phy[0] = '\0';
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#endif
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ehci = (struct usb_ehci *)CONFIG_SYS_FSL_USB_ADDR;
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*hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
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*hcor = (struct ehci_hcor *)((uint32_t) *hccr +
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HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
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/* Set to Host mode */
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setbits_le32(&ehci->usbmode, CM_HOST);
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out_be32(&ehci->snoop1, SNOOP_SIZE_2GB);
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out_be32(&ehci->snoop2, 0x80000000 | SNOOP_SIZE_2GB);
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/* Init phy */
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if (hwconfig_sub("usb1", "phy_type"))
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phy_type = hwconfig_subarg("usb1", "phy_type", &len);
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else
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phy_type = getenv("usb_phy_type");
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if (!phy_type) {
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#ifdef CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
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/* if none specified assume internal UTMI */
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strcpy(usb_phy, "utmi");
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phy_type = usb_phy;
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#else
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printf("WARNING: USB phy type not defined !!\n");
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return -1;
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#endif
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}
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if (!strcmp(phy_type, "utmi")) {
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#if defined(CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY)
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#if defined(CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE)
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ccsr_usb_phy_t *usb_phy =
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(void *)CONFIG_SYS_MPC85xx_USB1_PHY_ADDR;
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setbits_be32(&usb_phy->pllprg[1],
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CONFIG_SYS_FSL_USB_PLLPRG2_PHY2_CLK_EN |
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CONFIG_SYS_FSL_USB_PLLPRG2_PHY1_CLK_EN |
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CONFIG_SYS_FSL_USB_PLLPRG2_MFI |
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CONFIG_SYS_FSL_USB_PLLPRG2_PLL_EN);
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setbits_be32(&usb_phy->port1.ctrl,
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CONFIG_SYS_FSL_USB_CTRL_PHY_EN);
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setbits_be32(&usb_phy->port1.drvvbuscfg,
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CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN);
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setbits_be32(&usb_phy->port1.pwrfltcfg,
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CONFIG_SYS_FSL_USB_PWRFLT_CR_EN);
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setbits_be32(&usb_phy->port2.ctrl,
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CONFIG_SYS_FSL_USB_CTRL_PHY_EN);
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setbits_be32(&usb_phy->port2.drvvbuscfg,
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CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN);
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setbits_be32(&usb_phy->port2.pwrfltcfg,
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CONFIG_SYS_FSL_USB_PWRFLT_CR_EN);
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#endif
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setbits_be32(&ehci->control, PHY_CLK_SEL_UTMI);
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setbits_be32(&ehci->control, UTMI_PHY_EN);
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udelay(1000); /* delay required for PHY Clk to appear */
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#endif
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out_le32(&(*hcor)->or_portsc[0], PORT_PTS_UTMI);
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setbits_be32(&ehci->control, USB_EN);
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} else {
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setbits_be32(&ehci->control, PHY_CLK_SEL_ULPI);
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clrsetbits_be32(&ehci->control, UTMI_PHY_EN, USB_EN);
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udelay(1000); /* delay required for PHY Clk to appear */
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if (!usb_phy_clk_valid(ehci))
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return -EINVAL;
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out_le32(&(*hcor)->or_portsc[0], PORT_PTS_ULPI);
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}
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out_be32(&ehci->prictrl, 0x0000000c);
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out_be32(&ehci->age_cnt_limit, 0x00000040);
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out_be32(&ehci->sictrl, 0x00000001);
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in_le32(&ehci->usbmode);
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return 0;
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}
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/*
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* Destroy the appropriate control structures corresponding
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* the the EHCI host controller.
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*/
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int ehci_hcd_stop(int index)
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{
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return 0;
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}
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