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Benoît Thébaudeau b42b5b7a24 imx: mx6q DDR3 init: Fix MR0.PPD 
MR0.PPD should be set as in MMDCx_MDPDC.SLOW_PD, i.e. to fast-exit mode, which
is encoded as 1 in MRS.LMR.MR0.A12 and MMDCx_MDSCR[28].

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
2013-02-12 13:52:31 +01:00
..
mx6q_4x_mt41j128.cfg
imx: mx6q DDR3 init: Fix MR0.PPD
2013-02-12 13:52:31 +01:00