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b168591c89
There is no reason to specify header with full soc name. Symlink is setup automatically (arch -> arch-zynqmp) Signed-off-by: Michal Simek <michal.simek@xilinx.com>
147 lines
3.9 KiB
C
147 lines
3.9 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2015 Xilinx, Inc.
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*
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* Zynq USB HOST xHCI Controller
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*
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* Author: Siva Durga Prasad Paladugu<sivadur@xilinx.com>
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*
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* This file was reused from Freescale USB xHCI
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*/
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#include <common.h>
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#include <dm.h>
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#include <usb.h>
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#include <linux/errno.h>
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#include <asm/arch/hardware.h>
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#include <linux/compat.h>
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#include <linux/usb/dwc3.h>
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#include "xhci.h"
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/* Declare global data pointer */
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/* Default to the ZYNQMP XHCI defines */
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#define USB3_PWRCTL_CLK_CMD_MASK 0x3FE000
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#define USB3_PWRCTL_CLK_FREQ_MASK 0xFFC
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#define USB3_PHY_PARTIAL_RX_POWERON BIT(6)
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#define USB3_PHY_RX_POWERON BIT(14)
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#define USB3_PHY_TX_POWERON BIT(15)
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#define USB3_PHY_TX_RX_POWERON (USB3_PHY_RX_POWERON | USB3_PHY_TX_POWERON)
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#define USB3_PWRCTL_CLK_CMD_SHIFT 14
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#define USB3_PWRCTL_CLK_FREQ_SHIFT 22
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/* USBOTGSS_WRAPPER definitions */
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#define USBOTGSS_WRAPRESET BIT(17)
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#define USBOTGSS_DMADISABLE BIT(16)
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#define USBOTGSS_STANDBYMODE_NO_STANDBY BIT(4)
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#define USBOTGSS_STANDBYMODE_SMRT BIT(5)
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#define USBOTGSS_STANDBYMODE_SMRT_WKUP (0x3 << 4)
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#define USBOTGSS_IDLEMODE_NOIDLE BIT(2)
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#define USBOTGSS_IDLEMODE_SMRT BIT(3)
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#define USBOTGSS_IDLEMODE_SMRT_WKUP (0x3 << 2)
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/* USBOTGSS_IRQENABLE_SET_0 bit */
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#define USBOTGSS_COREIRQ_EN BIT(1)
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/* USBOTGSS_IRQENABLE_SET_1 bits */
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#define USBOTGSS_IRQ_SET_1_IDPULLUP_FALL_EN BIT(1)
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#define USBOTGSS_IRQ_SET_1_DISCHRGVBUS_FALL_EN BIT(3)
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#define USBOTGSS_IRQ_SET_1_CHRGVBUS_FALL_EN BIT(4)
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#define USBOTGSS_IRQ_SET_1_DRVVBUS_FALL_EN BIT(5)
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#define USBOTGSS_IRQ_SET_1_IDPULLUP_RISE_EN BIT(8)
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#define USBOTGSS_IRQ_SET_1_DISCHRGVBUS_RISE_EN BIT(11)
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#define USBOTGSS_IRQ_SET_1_CHRGVBUS_RISE_EN BIT(12)
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#define USBOTGSS_IRQ_SET_1_DRVVBUS_RISE_EN BIT(13)
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#define USBOTGSS_IRQ_SET_1_OEVT_EN BIT(16)
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#define USBOTGSS_IRQ_SET_1_DMADISABLECLR_EN BIT(17)
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struct zynqmp_xhci {
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struct usb_platdata usb_plat;
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struct xhci_ctrl ctrl;
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struct xhci_hccr *hcd;
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struct dwc3 *dwc3_reg;
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};
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struct zynqmp_xhci_platdata {
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fdt_addr_t hcd_base;
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};
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static int zynqmp_xhci_core_init(struct zynqmp_xhci *zynqmp_xhci)
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{
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int ret = 0;
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ret = dwc3_core_init(zynqmp_xhci->dwc3_reg);
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if (ret) {
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debug("%s:failed to initialize core\n", __func__);
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return ret;
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}
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/* We are hard-coding DWC3 core to Host Mode */
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dwc3_set_mode(zynqmp_xhci->dwc3_reg, DWC3_GCTL_PRTCAP_HOST);
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return ret;
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}
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void xhci_hcd_stop(int index)
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{
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/*
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* Currently zynqmp socs do not support PHY shutdown from
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* sw. But this support may be added in future socs.
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*/
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return;
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}
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static int xhci_usb_probe(struct udevice *dev)
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{
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struct zynqmp_xhci_platdata *plat = dev_get_platdata(dev);
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struct zynqmp_xhci *ctx = dev_get_priv(dev);
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struct xhci_hcor *hcor;
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int ret;
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ctx->hcd = (struct xhci_hccr *)plat->hcd_base;
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ctx->dwc3_reg = (struct dwc3 *)((char *)(ctx->hcd) + DWC3_REG_OFFSET);
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ret = zynqmp_xhci_core_init(ctx);
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if (ret) {
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puts("XHCI: failed to initialize controller\n");
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return -EINVAL;
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}
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hcor = (struct xhci_hcor *)((ulong)ctx->hcd +
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HC_LENGTH(xhci_readl(&ctx->hcd->cr_capbase)));
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return xhci_register(dev, ctx->hcd, hcor);
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}
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static int xhci_usb_remove(struct udevice *dev)
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{
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return xhci_deregister(dev);
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}
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static int xhci_usb_ofdata_to_platdata(struct udevice *dev)
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{
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struct zynqmp_xhci_platdata *plat = dev_get_platdata(dev);
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const void *blob = gd->fdt_blob;
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/* Get the base address for XHCI controller from the device node */
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plat->hcd_base = fdtdec_get_addr(blob, dev_of_offset(dev), "reg");
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if (plat->hcd_base == FDT_ADDR_T_NONE) {
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debug("Can't get the XHCI register base address\n");
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return -ENXIO;
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}
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return 0;
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}
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U_BOOT_DRIVER(dwc3_generic_host) = {
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.name = "dwc3-generic-host",
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.id = UCLASS_USB,
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.ofdata_to_platdata = xhci_usb_ofdata_to_platdata,
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.probe = xhci_usb_probe,
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.remove = xhci_usb_remove,
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.ops = &xhci_usb_ops,
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.platdata_auto_alloc_size = sizeof(struct zynqmp_xhci_platdata),
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.priv_auto_alloc_size = sizeof(struct zynqmp_xhci),
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.flags = DM_FLAG_ALLOC_PRIV_DMA,
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};
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