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This driver initializes PIC32 DDR2 SDRAM controller and internal DDR2 Phy module. DDR2 controller operates in half-rate mode (upto 533MHZ frequency). Signed-off-by: Paul Thacker <paul.thacker@microchip.com> Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
149 lines
3.0 KiB
C
149 lines
3.0 KiB
C
/*
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* (c) 2015 Purna Chandra Mandal <purna.mandal@microchip.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*
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*/
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#ifndef __MICROCHIP_DDR2_REGS_H
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#define __MICROCHIP_DDR2_REGS_H
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#include <linux/bitops.h>
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/* DDR2 Controller */
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struct ddr2_ctrl_regs {
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u32 tsel;
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u32 minlim;
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u32 reqprd;
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u32 mincmd;
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u32 memcon;
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u32 memcfg0;
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u32 memcfg1;
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u32 memcfg2;
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u32 memcfg3;
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u32 memcfg4;
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u32 refcfg;
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u32 pwrcfg;
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u32 dlycfg0;
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u32 dlycfg1;
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u32 dlycfg2;
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u32 dlycfg3;
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u32 odtcfg;
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u32 xfercfg;
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u32 cmdissue;
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u32 odtencfg;
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u32 memwidth;
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u32 unused[11];
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u32 cmd10[16];
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u32 cmd20[16];
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};
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/* Arbiter Config */
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#define MIN_LIM_WIDTH 5
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#define RQST_PERIOD_WIDTH 8
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#define MIN_CMDACPT_WIDTH 8
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/* Refresh Config */
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#define REFCNT_CLK(x) (x)
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#define REFDLY_CLK(x) ((x) << 16)
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#define MAX_PEND_REF(x) ((x) << 24)
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/* Power Config */
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#define PRECH_PWR_DN_ONLY(x) ((x) << 22)
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#define SELF_REF_DLY(x) ((x) << 12)
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#define PWR_DN_DLY(x) ((x) << 4)
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#define EN_AUTO_SELF_REF(x) ((x) << 3)
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#define EN_AUTO_PWR_DN(x) ((x) << 2)
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#define ERR_CORR_EN(x) ((x) << 1)
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#define ECC_EN(x) (x)
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/* Memory Width */
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#define HALF_RATE_MODE BIT(3)
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/* Delay Config */
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#define ODTWLEN(x) ((x) << 20)
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#define ODTRLEN(x) ((x) << 16)
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#define ODTWDLY(x) ((x) << 12)
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#define ODTRDLY(x) ((x) << 8)
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/* Xfer Config */
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#define BIG_ENDIAN(x) ((x) << 31)
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#define MAX_BURST(x) ((x) << 24)
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#define RDATENDLY(x) ((x) << 16)
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#define NXDATAVDLY(x) ((x) << 4)
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#define NXTDATRQDLY(x) ((x) << 0)
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/* Host Commands */
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#define IDLE_NOP 0x00ffffff
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#define PRECH_ALL_CMD 0x00fff401
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#define REF_CMD 0x00fff801
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#define LOAD_MODE_CMD 0x00fff001
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#define CKE_LOW 0x00ffeffe
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#define NUM_HOST_CMDS 12
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/* Host CMD Issue */
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#define CMD_VALID BIT(4)
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#define NUMHOSTCMD(x) (x)
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/* Memory Control */
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#define INIT_DONE BIT(1)
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#define INIT_START BIT(0)
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/* Address Control */
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#define EN_AUTO_PRECH 0
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#define SB_PRI 1
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/* DDR2 Phy Register */
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struct ddr2_phy_regs {
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u32 scl_start;
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u32 unused1[2];
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u32 scl_latency;
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u32 unused2[2];
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u32 scl_config_1;
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u32 scl_config_2;
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u32 pad_ctrl;
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u32 dll_recalib;
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};
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/* PHY PAD CONTROL */
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#define ODT_SEL BIT(0)
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#define ODT_EN BIT(1)
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#define DRIVE_SEL(x) ((x) << 2)
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#define ODT_PULLDOWN(x) ((x) << 4)
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#define ODT_PULLUP(x) ((x) << 6)
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#define EXTRA_OEN_CLK(x) ((x) << 8)
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#define NOEXT_DLL BIT(9)
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#define DLR_DFT_WRCMD BIT(13)
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#define HALF_RATE BIT(14)
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#define DRVSTR_PFET(x) ((x) << 16)
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#define DRVSTR_NFET(x) ((x) << 20)
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#define RCVR_EN BIT(28)
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#define PREAMBLE_DLY(x) ((x) << 29)
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/* PHY DLL RECALIBRATE */
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#define RECALIB_CNT(x) ((x) << 8)
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#define DISABLE_RECALIB(x) ((x) << 26)
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#define DELAY_START_VAL(x) ((x) << 28)
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/* PHY SCL CONFIG1 */
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#define SCL_BURST8 BIT(0)
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#define SCL_DDR_CONNECTED BIT(1)
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#define SCL_RCAS_LAT(x) ((x) << 4)
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#define SCL_ODTCSWW BIT(24)
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/* PHY SCL CONFIG2 */
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#define SCL_CSEN BIT(0)
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#define SCL_WCAS_LAT(x) ((x) << 8)
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/* PHY SCL Latency */
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#define SCL_CAPCLKDLY(x) ((x) << 0)
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#define SCL_DDRCLKDLY(x) ((x) << 4)
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/* PHY SCL START */
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#define SCL_START BIT(28)
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#define SCL_EN BIT(26)
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#define SCL_LUBPASS (BIT(1) | BIT(0))
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#endif /* __MICROCHIP_DDR2_REGS_H */
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