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332714b905
Use GUSBCFG_FORCEHOSTMODE to detected the HOST forced mode as it is done
in the Linux driver drivers/usb/dwc2/core.c:dwc2_core_reset().
The host polling must be executed only if the current mode is host,
either due to the force HOST mode (which persists after core reset)
or the connector id pin.
The GUSBCFG_FORCEDEVMODE bits is used to force the device mode (for
example used on STM32MP1x platform) and when it is activated the DWC2 reset
failed with the trace:
"dwc2_core_reset: Waiting for GINTSTS_CURMODE_HOST timeout"
Fixes: c5d685b8993c ("usb: dwc2: Unify flush and reset logic with v4.20a support")
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Junhui Liu <junhui.liu@pigmoral.tech>
Tested-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Marek Vasut <marek.vasut@mailbox.org>
132 lines
3.5 KiB
C
132 lines
3.5 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (c) 2024-2025, Kongyang Liu <seashell11234455@gmail.com>
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*/
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#include <linux/bitfield.h>
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#include <linux/errno.h>
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#include <linux/io.h>
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#include <wait_bit.h>
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#include "dwc2_core.h"
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int dwc2_core_reset(struct dwc2_core_regs *regs)
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{
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u32 snpsid;
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int ret;
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bool host_mode = false;
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if (!(readl(®s->global_regs.gotgctl) & GOTGCTL_CONID_B) ||
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(readl(®s->global_regs.gusbcfg) & GUSBCFG_FORCEHOSTMODE))
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host_mode = true;
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/* Core Soft Reset */
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snpsid = readl(®s->global_regs.gsnpsid);
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writel(GRSTCTL_CSFTRST, ®s->global_regs.grstctl);
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if (FIELD_GET(GSNPSID_VER_MASK, snpsid) < 0x420a) {
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ret = wait_for_bit_le32(®s->global_regs.grstctl, GRSTCTL_CSFTRST,
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false, 1000, false);
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if (ret) {
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log_warning("%s: Waiting for GRSTCTL_CSFTRST timeout\n", __func__);
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return ret;
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}
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} else {
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ret = wait_for_bit_le32(®s->global_regs.grstctl, GRSTCTL_CSFTRST_DONE,
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true, 1000, false);
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if (ret) {
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log_warning("%s: Waiting for GRSTCTL_CSFTRST_DONE timeout\n", __func__);
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return ret;
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}
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clrsetbits_le32(®s->global_regs.grstctl, GRSTCTL_CSFTRST, GRSTCTL_CSFTRST_DONE);
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}
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/* Wait for AHB master IDLE state. */
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ret = wait_for_bit_le32(®s->global_regs.grstctl, GRSTCTL_AHBIDLE,
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true, 1000, false);
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if (ret) {
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log_warning("%s: Waiting for GRSTCTL_AHBIDLE timeout\n", __func__);
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return ret;
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}
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if (host_mode) {
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ret = wait_for_bit_le32(®s->global_regs.gintsts, GINTSTS_CURMODE_HOST,
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host_mode, 1000, false);
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if (ret) {
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log_warning("%s: Waiting for GINTSTS_CURMODE_HOST timeout\n", __func__);
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return ret;
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}
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}
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return 0;
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}
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int dwc2_flush_tx_fifo(struct dwc2_core_regs *regs, const int num)
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{
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int ret;
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log_debug("Flush Tx FIFO %d\n", num);
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/* Wait for AHB master IDLE state */
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ret = wait_for_bit_le32(®s->global_regs.grstctl, GRSTCTL_AHBIDLE, true, 1000, false);
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if (ret) {
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log_warning("%s: Waiting for GRSTCTL_AHBIDLE timeout\n", __func__);
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return ret;
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}
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writel(GRSTCTL_TXFFLSH | FIELD_PREP(GRSTCTL_TXFNUM_MASK, num), ®s->global_regs.grstctl);
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ret = wait_for_bit_le32(®s->global_regs.grstctl, GRSTCTL_TXFFLSH, false, 1000, false);
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if (ret) {
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log_warning("%s: Waiting for GRSTCTL_TXFFLSH timeout\n", __func__);
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return ret;
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}
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/*
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* Wait for at least 3 PHY clocks.
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*
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* The PHY clock frequency can be configured to 6/30/48/60 MHz
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* based on the speed mode. A fixed delay of 1us ensures that the
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* wait time is sufficient even at the lowest PHY clock frequency
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* (6 MHz), where 1us corresponds to twice the duration of 3 PHY
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* clocks.
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*/
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udelay(1);
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return 0;
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}
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int dwc2_flush_rx_fifo(struct dwc2_core_regs *regs)
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{
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int ret;
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log_debug("Flush Rx FIFO\n");
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/* Wait for AHB master IDLE state */
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ret = wait_for_bit_le32(®s->global_regs.grstctl, GRSTCTL_AHBIDLE, true, 1000, false);
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if (ret) {
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log_warning("%s: Waiting for GRSTCTL_AHBIDLE timeout\n", __func__);
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return ret;
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}
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writel(GRSTCTL_RXFFLSH, ®s->global_regs.grstctl);
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ret = wait_for_bit_le32(®s->global_regs.grstctl, GRSTCTL_RXFFLSH, false, 1000, false);
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if (ret) {
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log_warning("%s: Waiting for GRSTCTL_RXFFLSH timeout\n", __func__);
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return ret;
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}
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/*
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* Wait for at least 3 PHY clocks.
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*
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* The PHY clock frequency can be configured to 6/30/48/60 MHz
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* based on the speed mode. A fixed delay of 1us ensures that the
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* wait time is sufficient even at the lowest PHY clock frequency
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* (6 MHz), where 1us corresponds to twice the duration of 3 PHY
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* clocks.
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*/
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udelay(1);
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return 0;
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}
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