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c8f5166cff
Put all slave CPUs (CPU1-3) into WFI mode. Master CPU (CPU0) writes the magic word into system manager's scratch register to indicate the system has performed L2 reset and request reset manager to perform hardware handshake and then trigger L2 reset. CPU0 put itself into WFI mode. L2 reset will reboot all HPS CPU cores after which all HPS cores are in WFI mode. L2 reset is followed by warm reset request by SPL via RMR_EL3 system register. Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com> Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
88 lines
1.9 KiB
C
88 lines
1.9 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2019 Pepperl+Fuchs
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* Copyright (C) 2025 Altera Corporation <www.altera.com>
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* Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
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*/
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#include <command.h>
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#include <cpu_func.h>
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#include <dm.h>
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#include <errno.h>
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#include <sysreset.h>
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#include <asm/arch/mailbox_s10.h>
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#include <asm/arch/reset_manager.h>
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#include <asm/secure.h>
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#define GICD_CTRL_ADDRESS 0xfffc1000
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static __always_inline void __l2_reset_cpu(void)
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{
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asm volatile(/* Disable GIC distributor (IRQs). */
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"str wzr, [%3]\n"
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/* Set Magic Number */
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"str %0, [%1]\n"
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/* Increase timeout in rstmgr.hdsktimeout */
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"ldr x2, =0xFFFFFF\n"
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"str w2, [%2, #0x64]\n"
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"ldr w2, [%2, #0x10]\n"
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/*
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* Set l2flushen = 1, etrstallen = 1,
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* fpgahsen = 1 and sdrselfrefen = 1
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* in rstmgr.hdsken to perform handshake
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* in certain peripherals before trigger
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* L2 reset.
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*/
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"ldr x3, =0x10D\n"
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"orr x2, x2, x3\n"
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"str w2, [%2, #0x10]\n"
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/* Trigger L2 reset in rstmgr.coldmodrst */
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"ldr w2, [%2, #0x34]\n"
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"orr x2, x2, #0x100\n"
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"isb\n"
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"dsb sy\n"
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"str w2, [%2, #0x34]\n"
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/* Put all cores into WFI mode */
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"1:\n"
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" wfi\n"
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" b 1b\n"
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: : "r" (L2_RESET_DONE_STATUS),
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"r" (L2_RESET_DONE_REG),
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"r" (SOCFPGA_RSTMGR_ADDRESS),
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"r" (GICD_CTRL_ADDRESS)
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: "x1", "x2", "x3");
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}
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static void l2_reset_cpu(void)
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{
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__l2_reset_cpu();
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}
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static int socfpga_sysreset_request(struct udevice *dev,
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enum sysreset_t type)
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{
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if (type == SYSRESET_WARM) {
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/* flush dcache */
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flush_dcache_all();
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/* request a warm reset */
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puts("Do warm reset now...\n");
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l2_reset_cpu();
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} else {
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puts("Mailbox: Issuing mailbox cmd REBOOT_HPS\n");
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mbox_reset_cold();
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}
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return -EINPROGRESS;
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}
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static struct sysreset_ops socfpga_sysreset = {
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.request = socfpga_sysreset_request,
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};
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U_BOOT_DRIVER(sysreset_socfpga) = {
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.id = UCLASS_SYSRESET,
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.name = "socfpga_sysreset",
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.ops = &socfpga_sysreset,
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};
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