mirror of
https://source.denx.de/u-boot/u-boot.git
synced 2025-12-20 00:41:29 +01:00
defe12f306
Samsung's S2MPU05 PMIC is used by Exynos7870 SoC. It has 5 buck and 38 LDO regulators. Add support for this device variant in the driver. Signed-off-by: Kaustabh Chakraborty <kauschluss@disroot.org> Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
293 lines
6.2 KiB
C
293 lines
6.2 KiB
C
#ifndef __S2MPS11__H__
|
|
#define __S2MPS11__H__
|
|
|
|
enum s2mps11_reg {
|
|
S2MPS11_REG_ID = 0,
|
|
S2MPS11_REG_INT1,
|
|
S2MPS11_REG_INT2,
|
|
S2MPS11_REG_INT3,
|
|
S2MPS11_REG_INT1M,
|
|
S2MPS11_REG_INT2M,
|
|
S2MPS11_REG_INT3M,
|
|
S2MPS11_REG_STATUS1,
|
|
S2MPS11_REG_STATUS2,
|
|
S2MPS11_REG_OFFSRC,
|
|
S2MPS11_REG_PWRONSRC,
|
|
S2MPS11_REG_RTC_CTRL,
|
|
S2MPS11_REG_CTRL1,
|
|
S2MPS11_REG_ETC_TEST,
|
|
S2MPS11_REG_RSVD3,
|
|
S2MPS11_REG_BU_CHG,
|
|
S2MPS11_REG_RAMP,
|
|
S2MPS11_REG_RAMP_BUCK,
|
|
S2MPS11_REG_LDO1_8,
|
|
S2MPS11_REG_LDO9_16,
|
|
S2MPS11_REG_LDO17_24,
|
|
S2MPS11_REG_LDO25_32,
|
|
S2MPS11_REG_LDO33_38,
|
|
S2MPS11_REG_LDO1_8_OVC,
|
|
S2MPS11_REG_LDO9_16_OVC,
|
|
S2MPS11_REG_LDO17_24_OVC,
|
|
S2MPS11_REG_LDO25_32_OVC,
|
|
S2MPS11_REG_LDO33_38_OVC,
|
|
S2MPS11_REG_RESERVED1,
|
|
S2MPS11_REG_RESERVED2,
|
|
S2MPS11_REG_RESERVED3,
|
|
S2MPS11_REG_RESERVED4,
|
|
S2MPS11_REG_RESERVED5,
|
|
S2MPS11_REG_RESERVED6,
|
|
S2MPS11_REG_RESERVED7,
|
|
S2MPS11_REG_RESERVED8,
|
|
S2MPS11_REG_WDRSTEN_CTRL,
|
|
S2MPS11_REG_B1CTRL1,
|
|
S2MPS11_REG_B1CTRL2,
|
|
S2MPS11_REG_B2CTRL1,
|
|
S2MPS11_REG_B2CTRL2,
|
|
S2MPS11_REG_B3CTRL1,
|
|
S2MPS11_REG_B3CTRL2,
|
|
S2MPS11_REG_B4CTRL1,
|
|
S2MPS11_REG_B4CTRL2,
|
|
S2MPS11_REG_B5CTRL1,
|
|
S2MPS11_REG_BUCK5_SW,
|
|
S2MPS11_REG_B5CTRL2,
|
|
S2MPS11_REG_B5CTRL3,
|
|
S2MPS11_REG_B5CTRL4,
|
|
S2MPS11_REG_B5CTRL5,
|
|
S2MPS11_REG_B6CTRL1,
|
|
S2MPS11_REG_B6CTRL2,
|
|
S2MPS11_REG_B7CTRL1,
|
|
S2MPS11_REG_B7CTRL2,
|
|
S2MPS11_REG_B8CTRL1,
|
|
S2MPS11_REG_B8CTRL2,
|
|
S2MPS11_REG_B9CTRL1,
|
|
S2MPS11_REG_B9CTRL2,
|
|
S2MPS11_REG_B10CTRL1,
|
|
S2MPS11_REG_B10CTRL2,
|
|
S2MPS11_REG_L1CTRL,
|
|
S2MPS11_REG_L2CTRL,
|
|
S2MPS11_REG_L3CTRL,
|
|
S2MPS11_REG_L4CTRL,
|
|
S2MPS11_REG_L5CTRL,
|
|
S2MPS11_REG_L6CTRL,
|
|
S2MPS11_REG_L7CTRL,
|
|
S2MPS11_REG_L8CTRL,
|
|
S2MPS11_REG_L9CTRL,
|
|
S2MPS11_REG_L10CTRL,
|
|
S2MPS11_REG_L11CTRL,
|
|
S2MPS11_REG_L12CTRL,
|
|
S2MPS11_REG_L13CTRL,
|
|
S2MPS11_REG_L14CTRL,
|
|
S2MPS11_REG_L15CTRL,
|
|
S2MPS11_REG_L16CTRL,
|
|
S2MPS11_REG_L17CTRL,
|
|
S2MPS11_REG_L18CTRL,
|
|
S2MPS11_REG_L19CTRL,
|
|
S2MPS11_REG_L20CTRL,
|
|
S2MPS11_REG_L21CTRL,
|
|
S2MPS11_REG_L22CTRL,
|
|
S2MPS11_REG_L23CTRL,
|
|
S2MPS11_REG_L24CTRL,
|
|
S2MPS11_REG_L25CTRL,
|
|
S2MPS11_REG_L26CTRL,
|
|
S2MPS11_REG_L27CTRL,
|
|
S2MPS11_REG_L28CTRL,
|
|
S2MPS11_REG_L29CTRL,
|
|
S2MPS11_REG_L30CTRL,
|
|
S2MPS11_REG_L31CTRL,
|
|
S2MPS11_REG_L32CTRL,
|
|
S2MPS11_REG_L33CTRL,
|
|
S2MPS11_REG_L34CTRL,
|
|
S2MPS11_REG_L35CTRL,
|
|
S2MPS11_REG_L36CTRL,
|
|
S2MPS11_REG_L37CTRL,
|
|
S2MPS11_REG_L38CTRL,
|
|
S2MPS11_REG_COUNT,
|
|
};
|
|
|
|
#define S2MPS11_LDO26_ENABLE 0xec
|
|
|
|
/* Driver name */
|
|
#define S2MPS11_BUCK_DRIVER "s2mps11_buck"
|
|
#define S2MPS11_OF_BUCK_PREFIX "BUCK"
|
|
#define S2MPS11_LDO_DRIVER "s2mps11_ldo"
|
|
#define S2MPS11_OF_LDO_PREFIX "LDO"
|
|
|
|
/* BUCK */
|
|
#define S2MPS11_BUCK_VOLT_MASK 0xff
|
|
#define S2MPS11_BUCK9_VOLT_MASK 0x1f
|
|
|
|
#define S2MPS11_BUCK_LSTEP 6250
|
|
#define S2MPS11_BUCK_HSTEP 12500
|
|
#define S2MPS11_BUCK9_STEP 25000
|
|
|
|
#define S2MPS11_BUCK_UV_MIN 600000
|
|
#define S2MPS11_BUCK_UV_HMIN 750000
|
|
#define S2MPS11_BUCK9_UV_MIN 1400000
|
|
|
|
#define S2MPS11_BUCK_VOLT_MAX_HEX 0xA0
|
|
#define S2MPS11_BUCK5_VOLT_MAX_HEX 0xDF
|
|
#define S2MPS11_BUCK7_8_10_VOLT_MAX_HEX 0xDC
|
|
#define S2MPS11_BUCK9_VOLT_MAX_HEX 0x5F
|
|
|
|
#define S2MPS11_BUCK_MODE_SHIFT 6
|
|
#define S2MPS11_BUCK_MODE_MASK (0x3)
|
|
#define S2MPS11_BUCK_MODE_OFF (0x0 << 6)
|
|
#define S2MPS11_BUCK_MODE_STANDBY (0x1 << 6)
|
|
#define S2MPS11_BUCK_MODE_ON (0x3 << 6)
|
|
|
|
/* LDO */
|
|
#define S2MPS11_LDO_VOLT_MASK 0x3F
|
|
#define S2MPS11_LDO_VOLT_MAX_HEX 0x3F
|
|
|
|
#define S2MPS11_LDO_STEP 25000
|
|
#define S2MPS11_LDO_UV_MIN 800000
|
|
|
|
#define S2MPS11_LDO_MODE_MASK 0x3
|
|
#define S2MPS11_LDO_MODE_SHIFT 6
|
|
|
|
#define S2MPS11_LDO_MODE_OFF (0x0 << 6)
|
|
#define S2MPS11_LDO_MODE_STANDBY (0x1 << 6)
|
|
#define S2MPS11_LDO_MODE_STANDBY_LPM (0x2 << 6)
|
|
#define S2MPS11_LDO_MODE_ON (0x3 << 6)
|
|
|
|
enum s2mpu05_reg {
|
|
S2MPU05_REG_ID,
|
|
S2MPU05_REG_INT1,
|
|
S2MPU05_REG_INT2,
|
|
S2MPU05_REG_INT3,
|
|
S2MPU05_REG_INT1M,
|
|
S2MPU05_REG_INT2M,
|
|
S2MPU05_REG_INT3M,
|
|
S2MPU05_REG_ST1,
|
|
S2MPU05_REG_ST2,
|
|
S2MPU05_REG_PWRONSRC,
|
|
S2MPU05_REG_OFFSRC,
|
|
S2MPU05_REG_BU_CHG,
|
|
S2MPU05_REG_RTC_BUF,
|
|
S2MPU05_REG_CTRL1,
|
|
S2MPU05_REG_CTRL2,
|
|
S2MPU05_REG_ETC_TEST,
|
|
S2MPU05_REG_OTP_ADRL,
|
|
S2MPU05_REG_OTP_ADRH,
|
|
S2MPU05_REG_OTP_DATA,
|
|
S2MPU05_REG_MON1SEL,
|
|
S2MPU05_REG_MON2SEL,
|
|
S2MPU05_REG_CTRL3,
|
|
S2MPU05_REG_ETC_OTP,
|
|
S2MPU05_REG_UVLO,
|
|
S2MPU05_REG_TIME_CTRL1,
|
|
S2MPU05_REG_TIME_CTRL2,
|
|
S2MPU05_REG_B1CTRL1,
|
|
S2MPU05_REG_B1CTRL2,
|
|
S2MPU05_REG_B2CTRL1,
|
|
S2MPU05_REG_B2CTRL2,
|
|
S2MPU05_REG_B2CTRL3,
|
|
S2MPU05_REG_B2CTRL4,
|
|
S2MPU05_REG_B3CTRL1,
|
|
S2MPU05_REG_B3CTRL2,
|
|
S2MPU05_REG_B3CTRL3,
|
|
S2MPU05_REG_B4CTRL1,
|
|
S2MPU05_REG_B4CTRL2,
|
|
S2MPU05_REG_B5CTRL1,
|
|
S2MPU05_REG_B5CTRL2,
|
|
S2MPU05_REG_BUCK_RAMP,
|
|
S2MPU05_REG_LDO_DVS1,
|
|
S2MPU05_REG_LDO_DVS9,
|
|
S2MPU05_REG_LDO_DVS10,
|
|
S2MPU05_REG_L1CTRL,
|
|
S2MPU05_REG_L2CTRL,
|
|
S2MPU05_REG_L3CTRL,
|
|
S2MPU05_REG_L4CTRL,
|
|
S2MPU05_REG_L5CTRL,
|
|
S2MPU05_REG_L6CTRL,
|
|
S2MPU05_REG_L7CTRL,
|
|
S2MPU05_REG_L8CTRL,
|
|
S2MPU05_REG_L9CTRL1,
|
|
S2MPU05_REG_L9CTRL2,
|
|
S2MPU05_REG_L10CTRL,
|
|
S2MPU05_REG_L11CTRL1,
|
|
S2MPU05_REG_L11CTRL2,
|
|
S2MPU05_REG_L12CTRL,
|
|
S2MPU05_REG_L13CTRL,
|
|
S2MPU05_REG_L14CTRL,
|
|
S2MPU05_REG_L15CTRL,
|
|
S2MPU05_REG_L16CTRL,
|
|
S2MPU05_REG_L17CTRL1,
|
|
S2MPU05_REG_L17CTRL2,
|
|
S2MPU05_REG_L18CTRL1,
|
|
S2MPU05_REG_L18CTRL2,
|
|
S2MPU05_REG_L19CTRL,
|
|
S2MPU05_REG_L20CTRL,
|
|
S2MPU05_REG_L21CTRL,
|
|
S2MPU05_REG_L22CTRL,
|
|
S2MPU05_REG_L23CTRL,
|
|
S2MPU05_REG_L24CTRL,
|
|
S2MPU05_REG_L25CTRL,
|
|
S2MPU05_REG_L26CTRL,
|
|
S2MPU05_REG_L27CTRL,
|
|
S2MPU05_REG_L28CTRL,
|
|
S2MPU05_REG_L29CTRL,
|
|
S2MPU05_REG_L30CTRL,
|
|
S2MPU05_REG_L31CTRL,
|
|
S2MPU05_REG_L32CTRL,
|
|
S2MPU05_REG_L33CTRL,
|
|
S2MPU05_REG_L34CTRL,
|
|
S2MPU05_REG_L35CTRL,
|
|
S2MPU05_REG_LDO_DSCH1,
|
|
S2MPU05_REG_LDO_DSCH2,
|
|
S2MPU05_REG_LDO_DSCH3,
|
|
S2MPU05_REG_LDO_DSCH4,
|
|
S2MPU05_REG_LDO_DSCH5,
|
|
S2MPU05_REG_LDO_CTRL1,
|
|
S2MPU05_REG_LDO_CTRL2,
|
|
S2MPU05_REG_TCXO_CTRL,
|
|
S2MPU05_REG_SELMIF,
|
|
S2MPU05_REG_COUNT,
|
|
};
|
|
|
|
#define S2MPU05_OF_BUCK_PREFIX "buck"
|
|
#define S2MPU05_OF_LDO_PREFIX "ldo"
|
|
|
|
/* BUCK */
|
|
#define S2MPU05_BUCK_MIN1 400000
|
|
#define S2MPU05_BUCK_MIN2 600000
|
|
#define S2MPU05_BUCK_STEP1 6250
|
|
#define S2MPU05_BUCK_STEP2 12500
|
|
|
|
/* LDO */
|
|
#define S2MPU05_LDO_MIN1 800000
|
|
#define S2MPU05_LDO_MIN2 1800000
|
|
#define S2MPU05_LDO_MIN3 400000
|
|
#define S2MPU05_LDO_STEP1 12500
|
|
#define S2MPU05_LDO_STEP2 25000
|
|
|
|
struct sec_regulator_desc {
|
|
/* regulator mode control */
|
|
unsigned int mode_reg;
|
|
unsigned int mode_mask;
|
|
|
|
/* regulator voltage control */
|
|
unsigned int volt_reg;
|
|
unsigned int volt_mask;
|
|
|
|
unsigned int volt_min;
|
|
unsigned int volt_step;
|
|
unsigned int volt_max_hex;
|
|
};
|
|
|
|
enum {
|
|
OP_OFF = 0,
|
|
OP_LPM,
|
|
OP_STANDBY,
|
|
OP_STANDBY_LPM,
|
|
OP_ON,
|
|
};
|
|
|
|
enum {
|
|
VARIANT_NONE,
|
|
VARIANT_S2MPS11,
|
|
VARIANT_S2MPU05,
|
|
};
|
|
|
|
#endif
|