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11da3403e9
For nearly all commands in U-Boot the '?' variable is handled the same way with 0 meaning success, 1 meaning any failure. Explain this in the general rules section of the cmdline documentation (with a link to a counter example) and then remove the redundant wording from most commands. We retain a section about the return value in a number of places where we are doing something such as always returning a specific value or we have useful additional information to go along with the normal return codes. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
96 lines
2.2 KiB
ReStructuredText
96 lines
2.2 KiB
ReStructuredText
.. SPDX-License-Identifier: GPL-2.0+
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.. Copyright 2024 NXP
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.. index::
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single: cpu (command)
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cpu command
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===========
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Synopsis
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--------
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::
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cpu list
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cpu detail
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cpu release <core ID> <addr>
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Description
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-----------
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The *cpu* command prints information about the CPUs, and release a CPU core
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to a given address to run applications.
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cpu list
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~~~~~~~~
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The 'list' subcommand lists and prints brief information of all the CPU cores,
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the CPU information is provided by vendors' CPU driver.
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cpu detail
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~~~~~~~~~~
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The 'detail' subcommand prints more details about the CPU cores, including
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CPU ID, core frequency and feature list.
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cpu release
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~~~~~~~~~~~
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The 'release' subcommand is used to release a CPU core to run a baremetal or
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RTOS applications.
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The parameter <core ID> is the sequence number of the CPU core to release.
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The parameter <addr> is the address to run of the specified core after release.
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Examples
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--------
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cpu list
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~~~~~~~~
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This example lists all the CPU cores On i.MX8M Plus EVK:
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::
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u-boot=> cpu list
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0: cpu@0 NXP i.MX8MP Rev1.1 A53 at 1200 MHz at 31C
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1: cpu@1 NXP i.MX8MP Rev1.1 A53 at 1200 MHz at 30C
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2: cpu@2 NXP i.MX8MP Rev1.1 A53 at 1200 MHz at 31C
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3: cpu@3 NXP i.MX8MP Rev1.1 A53 at 1200 MHz at 31C
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cpu detail
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~~~~~~~~~~
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This example prints the details of the CPU cores On i.MX8M Plus EVK:
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::
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u-boot=> cpu detail
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0: cpu@0 NXP i.MX8MP Rev1.1 A53 at 1200 MHz at 31C
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ID = 0, freq = 1.2 GHz: L1 cache, MMU
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1: cpu@1 NXP i.MX8MP Rev1.1 A53 at 1200 MHz at 30C
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ID = 0, freq = 1.2 GHz: L1 cache, MMU
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2: cpu@2 NXP i.MX8MP Rev1.1 A53 at 1200 MHz at 31C
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ID = 0, freq = 1.2 GHz: L1 cache, MMU
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3: cpu@3 NXP i.MX8MP Rev1.1 A53 at 1200 MHz at 31C
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ID = 0, freq = 1.2 GHz: L1 cache, MMU
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cpu release
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~~~~~~~~~~~
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This example shows release the LAST CPU core to run a RTOS application, on
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i.MX8M Plus EVK:
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::
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u-boot=> load mmc 1:2 c0000000 /hello_world.bin
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66008 bytes read in 5 ms (12.6 MiB/s)
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u-boot=> dcache flush; icache flush
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u-boot=> cpu release 3 c0000000
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Released CPU core (mpidr: 0x3) to address 0xc0000000
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Configuration
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-------------
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The cpu command is available if CONFIG_CMD_CPU=y.
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