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Introduce a new version of the Keystone-II "ddr" command for testing the inline ECC support in the DDRSS bridge available on K3 devices. The ECC hardware support in K3's DDRSS and the test method differ substantially from what we support in the K2 variant of the command. This K3 DDRSS command currently supports only single controller testing. The ECC error injection procedure follows these steps: 1) Flush and disable the data cache. 2) Disable the protected ECC Rx range. 3) Flip a bit in the address. 4) Restore the range to original. 5) Read the modified value (corrected). 6) Re-enable the data cache. This will cause the 1-bit ECC error count to increase while the read will return the corrected value. The K3 version of the command extends the syntax for the "ecc_err" argument by also introducing an argument for range which specifies which range (0, 1, 2) the address is located in. Multi-bit ECC errors are uncorrectable and will lead to a synchronous abort. Signed-off-by: Georgi Vlaev <g-vlaev@ti.com> Signed-off-by: Santhosh Kumar K <s-k6@ti.com> [n-francis@ti.com: Add J7 and multiple-region support, simplify logic] Signed-off-by: Neha Malcom Francis <n-francis@ti.com> Reviewed-by: Udit Kumar <u-kumar1@ti.com>