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337bc26f05
The NPCM driver can use on npcm7xx/npcm8xx so add npcm8xx header for driver. Signed-off-by: Jim Liu <JJLIU0@nuvoton.com>
44 lines
1.2 KiB
C
44 lines
1.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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#ifndef _NPCM_RNG_H_
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#define _NPCM_RNG_H_
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struct npcm_rng_regs {
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unsigned int rngcs;
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unsigned int rngd;
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unsigned int rngmode;
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};
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#define RNGCS_RNGE (1 << 0)
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#define RNGCS_DVALID (1 << 1)
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#define RNGCS_CLKP(range) ((0x0f & (range)) << 2)
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#define RNGMODE_M1ROSEL_VAL (0x02) /* Ring Oscillator Select for Method I */
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/*----------------------------------------------------------------------------*/
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/* Core Domain Clock Frequency Range for the selected value is higher */
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/* than or equal to the actual Core domain clock frequency */
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/*----------------------------------------------------------------------------*/
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enum {
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RNG_CLKP_80_100_MHZ = 0x00, /*default */
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RNG_CLKP_60_80_MHZ = 0x01,
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RNG_CLKP_50_60_MHZ = 0x02,
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RNG_CLKP_40_50_MHZ = 0x03,
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RNG_CLKP_30_40_MHZ = 0x04,
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RNG_CLKP_25_30_MHZ = 0x05,
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RNG_CLKP_20_25_MHZ = 0x06,
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RNG_CLKP_5_20_MHZ = 0x07,
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RNG_CLKP_2_15_MHZ = 0x08,
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RNG_CLKP_9_12_MHZ = 0x09,
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RNG_CLKP_7_9_MHZ = 0x0A,
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RNG_CLKP_6_7_MHZ = 0x0B,
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RNG_CLKP_5_6_MHZ = 0x0C,
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RNG_CLKP_4_5_MHZ = 0x0D,
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RNG_CLKP_3_4_MHZ = 0x0E,
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RNG_NUM_OF_CLKP
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};
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void npcm_rng_init(void);
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void npcm_rng_disable(void);
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#endif
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